Abstract: Embodiments of the present disclosure generally relate to substrate support assemblies used in semiconductor device manufacturing. In one embodiment, a substrate support includes a ceramic body having at least one aperture formed therein defined by a sidewall. A plurality of recesses extend into the sidewall, a rod member is disposed in the at least one aperture, and an eyelet member is circumferentially disposed about the rod member. The eyelet member has a plurality of protrusions extending outwardly therefrom, each disposed in a corresponding recess of the plurality of recesses. A first portion of each protrusion is in contact with a sidewall of the respective recess of the ceramic body and a second portion of each protrusion is separated by a gap from the sidewall of the respective recess of the ceramic body. A first portion of a brazing material is disposed between an upper surface of the at least one aperture and an end of the rod member.

Abstract: A system includes a robot arm with multiple joints and one or more end effector to carry a substrate. A processing device determines, within joint space of the robot arm, start/end points of the one or more end effector for a complete movement. The processing device builds, in joint space for the multiple joints and the one or more end effector, a graph of reachable positions and sub-paths between the reachable positions that satisfy Cartesian limits. The reachable positions are identified at a granularity that divides the complete movement into multiple sub-movements. The processing device executes a graph optimization algorithm on the graph to determine multiple paths, each a group of the sub-paths, that have one of shortest distances or lowest costs between the start/end points, and selects a path thereof that minimizes move time of the one or more end effector between the start/end points.

Abstract: Embodiments described herein relate to a precision dynamic leveling mechanism for repeatedly positioning the pedestal within a process. The precision dynamic leveling mechanism includes bearing assemblies. Bearing assemblies having inner races forced against a pedestal assembly carrier and outer races forced against a guide adaptor provide nominal clearance between the inner races and outer races to allow the inner races and the outer races to slide on each other with minimal or no radial motion.

Abstract: Exemplary methods of etching may include flowing a fluorine-containing precursor and a secondary gas into a processing region of a semiconductor processing chamber. The secondary gas may be or include oxygen or nitrogen. A flow rate ratio of the fluorine-containing precursor to the secondary gas may be greater than or about 1:1. The methods may include contacting a substrate with the fluorine-containing precursor and the secondary gas. The substrate may include an exposed metal. The substrate may define a high aspect-ratio structure. The methods may include etching the exposed metal within the high aspect-ratio structure.

Abstract: Power supplies, waveform function generators and methods for controlling a plasma process are described. The power supplies or waveform function generators include a component for executing the method in which a waveform shape change index is determined during a plasma process and evaluated for compliance with a predetermined tolerance.

Abstract: A network-on-package (NoPK) for connecting a plurality of chiplets may include a plurality of interface bridges configured to convert a plurality of protocols used by the plurality of chiplets into a common protocol, a routing network configured to route traffic between the plurality of interface bridges using the common protocol, and a controller configured to program the plurality of interface bridges and the routing network based on types of the plurality of chiplets connected to the NoPK. The NoPK may provide a scalable connection for any number of chiplets from different ecosystems using different communication protocols.

Abstract: Pump liners and process chambers with the pump liners are described. The pump liner has a ring-shaped body with an annular wall enclosing a process region. A plurality of circumferentially spaced openings provide fluid communication through the annular wall between the process region and a region outside of the ring-shaped body. Each of the plurality of circumferentially spaced openings has a self-adjusting valve assembly. Self-adjusting valves and processing methods are also described.

Abstract: Methods for patterning a substrate are described. A substrate is scanned using a spatial light modulator with a plurality of exposures timed according to a non-crystalline shot pattern. Lithography systems for performing the substrate patterning method and non-transitory computer-readable medium for executing the patterning method are also described.

Abstract: Methods, systems and apparatus for decreasing total distortion of a maskless lithography process are disclosed. Some embodiments provide methods, systems and apparatus for decreasing total distortion without physical modification of the apparatus.

Abstract: Approaches herein decrease nanosheet gate length variations by implanting a gate layer material with ions prior to etching. A method may include forming a dummy gate structure over a nanosheet stack, the dummy gate structure including a hardmask atop a gate material layer, and removing a portion of the hardmask to expose a first area and a second area of the gate material layer. The method may further include implanting the dummy gate structure to modify the first and second areas of the gate material layer, and etching the first and second areas of the gate material layer to form a treated layer along a sidewall of a third area of the gate material layer, wherein the third area is beneath the hardmask.

Abstract: Molybdenum(0) and coordination complexes are described. Methods for depositing molybdenum-containing films on a substrate are described. The substrate is exposed to a molybdenum precursor and a reactant to form the molybdenum-containing film (e.g., elemental molybdenum, molybdenum oxide, molybdenum carbide, molybdenum silicide, molybdenum disulfide, molybdenum nitride). The exposures can be sequential or simultaneous.

Abstract: Methods of forming memory devices are described. A molybdenum silicide nucleation layer is formed, and the substrate is soaked in a titanium precursor prior to a bulk molybdenum gap fill process. In other embodiments, a molybdenum silicide film is formed in a first process cycle and a second process cycle is performed where the substrate is exposed to a titanium precursor. In further embodiments, a substrate having at least one feature thereon is exposed to a first titanium precursor and a nitrogen-containing reactant. The substrate is then soaked in a second titanium precursor, and then is exposed to a first molybdenum precursor followed by exposure to a silane to form a molybdenum silicide layer on a surface of the substrate.

Abstract: A method of forming a metal oxide semiconductor field effect transistor with improved gate-induced drain leakage performance, the method including providing a semiconductor substrate having a gate trench formed therein, performing an ion implantation process on upper portions of sidewalls of the gate trench to make the upper portions more susceptible to oxidation relative to non-implanted lower portions of the sidewalls, and performing an oxidation process on surfaces of the substrate, wherein the implanted upper portions of the sidewalls develop a thicker layer of oxidation relative to the non-implanted lower portions of the sidewalls.

Abstract: Methods for forming a semiconductor structure are described. The method includes cleaning a substrate to form a substrate surface substantially free of oxide, exposing the substrate surface to a first molybdenum precursor, and exposing the substrate surface to a reactant to selectively deposit a first molybdenum film on the substrate surface. The method may be performed in a processing chamber without breaking vacuum. The method may also include forming one or more of a cap layer and a liner and annealing the substrate. The method may also include depositing a second molybdenum film on the substrate surface.

Abstract: An extreme ultraviolet mask and method of manufacture thereof includes: providing a glass-ceramic block; forming a glass-ceramic substrate from the glass-ceramic block; and depositing a planarization layer on the glass-ceramic substrate.

Abstract: Horizontal gate-all-around devices and methods of manufacturing same are described. The hGAA devices comprise a doped semiconductor material between source regions and drain regions of the device. The method includes doping semiconductor material layers between source regions and drain regions of an electronic device.

Abstract: Exemplary substrate support assemblies include an electrostatic chuck body defining a substrate platform. The substrate platform may be characterized by an upper surface. The platform may define a purge aperture. The platform may include a plurality of mesas that are disposed in an inner region of the upper surface. Each of the mesas may protrude upward from the upper surface. The platform may include a sealing band that extends upward from the upper surface in a circumferential pattern and partially encircles the inner region of the upper surface. Top surfaces of the mesas and sealing band may form a support surface for a substrate. The sealing band may define a number of gaps. The assemblies may include a support stem coupled with the electrostatic chuck body, a heater embedded within the electrostatic chuck body, and a backside gas source that is coupled with the purge aperture of the support surface.

Abstract: Embodiments of this disclosure include a method of processing a substrate that includes etching a first dielectric material formed on a substrate that is disposed on a substrate supporting surface of a substrate support assembly disposed within a processing region of a plasma processing chamber. The etching process may include delivering a process gas to the processing region, wherein the process gas comprises a first fluorocarbon containing gas and a first process gas, delivering, by use of a radio frequency generator, a radio frequency signal to a first electrode to form a plasma in the processing region, and establishing, by use of a first pulsed-voltage waveform generator, a first pulsed voltage waveform at a biasing electrode disposed within the substrate support assembly.

Abstract: A pedestal for a thermal treatment chamber is disclosed that includes a body consisting of an optically transparent material. The body includes a first plate with a perforated surface having a plurality of nozzles formed therein, a first portion of the plurality nozzles formed in the body at an angle that is orthogonal to a plane of the first plate, a second portion of the plurality of nozzles formed in the body in an azimuthal orientation and at an acute angle relative to the plane of the first plate, and a third portion of the plurality nozzles formed in the body in a radial orientation and at an acute angle relative to the plane of the first plate.

Abstract: An ion beam processing system including a plasma chamber, a plasma plate, disposed alongside the plasma chamber, the plasma plate defining a first extraction aperture, a beam blocker, disposed within the plasma chamber and facing the extraction aperture, a blocker electrode, disposed on a surface of the beam blocker outside of the plasma chamber, and an extraction electrode disposed on a surface of the plasma plate outside of the plasma chamber.