Abstract: A circuit includes a phase lock loop circuit and a continuous phase lock loop calibration circuit. The continuous phase lock loop calibration circuit is operatively coupled to the PLL circuit and produces a continuous calibration signal based on a reference voltage from a reference voltage circuit to calibrate the PLL circuit on a continuous basis.

Abstract: A method of determining when cable modems in a distributed digital data delivery service over cable TV hybrid fiber coaxial cable network have a headroom problem and resolving said problem. The method involves measuring the burst power from each cable modem, and if the burst power is too low, requesting the cable modem whose burst power is too low to increase its transmit power, and keeping track of which modems have been requested to increase their power. If a predetermined number of requests to increase power have not resulted in the cable modem transmitting with sufficient power for reliable reception, the cable modem is listed as having a headroom problem. Subsequent requests for upstream bandwidth from all modems with headroom problems are analyzed to determine if the requested burst size is too large and will result in a headroom problem. If so, a calculation as to the maximum number of spreading codes that each modem with a headroom problem can simultaneously transmit on without a headroom problem.

Abstract: A method for rendering pixels for display includes generating stencil values on a per pixel basis for storage in stencil buffer memory; selecting a group of stencil values that represent a block of pixels; generating compressed stencil data associated with the group of stencil values; and performing stencil testing on a corresponding incoming block of pixels using the compressed stencil data.

Abstract: A method for processing video image data including a plurality of different image data types begins by providing tasks to be performed on each different image data type. The image data is divided into a plurality of groups based on the image data type. A set of arithmetic operations required to accomplish the tasks provided for the corresponding image data type is determined. Each arithmetic operation is assigned to one of a plurality of commonly used arithmetic units which performs the arithmetic operation, whereby each image data type is transformed in accordance with the corresponding provided tasks. The transformed image data of each group is combined, completing the processing.

Abstract: A method and apparatus for generating hierarchical depth culling characteristics includes determining a first minimum depth value and a first maximum depth value for a first graphical element. The graphical element may be a primitive. The first minimum depth value may be a minimum Z-plane depth of a pixel within the primitive and a first maximum depth value is a maximum Z-plane value for a pixel within the primitive. The method and apparatus further includes determining a second minimum depth value and a second maximum depth value for a second graphical element, which may be a tile. The method and apparatus further includes calculating an intersection depth range having an intersection minimum depth value and an intersection maximum depth value based on the intersection of the first minimum depth value and the first maximum depth value and the second minimum depth value and the second maximum depth value.

Abstract: In accordance with a specific aspect of the present invention, a compressed video stream, such as an MPEG-2 video stream, is received by a transport demultiplexor, synchronized, parsed into separate packet types, and written to buffer locations external the demultiplexor. Adaptation field is handled by a separate parser. In addition, primary elementary stream data can be handled by separate primary elementary stream parsers based upon the packet identifier of the primary elementary stream. Video packets can be parsed based upon stream identifier values. Specific packets of data are stored in one or more system memory or video memory buffers by an output controller based upon allocation table information. Private data associated with specific elementary streams or packet adaptation fields are repacketized, and written to an output buffer location. In specific implementations, the hardware associated with the system is used to acquire the data stream without any knowledge of the specific protocol of the stream.

Abstract: Graphics processing circuitry includes processing circuitry operative to generate pixel information in response to primitive information, and a correction circuit, coupled to the processing circuitry, operative to generate gamma corrected pixel information in response to the pixel information. The correction circuit converts the floating point pixel information generated by the processing circuitry into a gamma corrected fixed-point value so that gamma space pixel data is stored in the frame buffer. This fixed point gamma corrected pixel information, converted from the floating point pixel information, compensates for the non-linear display characteristics exhibited by current display devices. This results in the display output being more accurate; thereby, improving the appearance quality of the resulting image.

Abstract: A method of graphics processing includes determining a non-depth conditional status and an occlusion status of a fragment. Such a method may be used in culling occluded fragments before expending resources such as processing cycles and memory bus usage. In one example, a scratchpad stores depth values of robust fragments and is used for occlusion testing. Graphics architectures, and methods that include use of representative Z values, are also disclosed.

Abstract: Briefly, a method, apparatus and system for managing power corresponding to a differential serial communication link that has a link width defined for example by one or more lanes wherein the lanes are adapted to communicate clock recovery information in a data stream, determines, during normal operating conditions, such as conditions other than power on, reset or link fault conditions, a desired link width for the serial communication link and then changes the link width accordingly.

Abstract: A variable clock control information generator receives vertical blank interval information corresponding to a vertical blank interval (VBI) during display rasterization. The vertical blank interval is a period of time in a video display signal that temporarily suspends transmission of video data as is known during display rasterization, to allow a display to return back up to (retrace) the first line of the display after scanning the end of the display. In response to the received vertical blank interval information, the variable clock control information generator produces memory clock control information to change the frequency of a memory clock divider signal during the detected vertical blank interval.

Abstract: A system and methods are provided for processing graphics to be displayed in a portable device. A current mode of operation of the portable device is identified. In a normal mode of operation, image data associated with the portable device is rendered by a graphics system of the portable device and stored in memory external to the graphics system prior to display. When a screen refresh mode of operation is identified, image data rendered by the graphics system is compressed and stored in memory integrated internal to the graphics system. The present disclosure has the advantage of allowing the memory external to the graphics system to be disabled during the screen refresh mode of operation, reducing power consumed by the portable device.

Abstract: In accordance with a specific aspect of the present invention, a compressed video stream, such as an MPEG-2 video stream, is received by a transport demultiplexor, synchronized, parsed into separate packet types, and written to buffer locations external the demultiplexor. Adaptation field is handled by a separate parser. In addition, primary elementary stream data can be handled by separate primary elementary stream parsers based upon the packet identifier of the primary elementary stream. Video packets can be parsed based upon stream identifier values. Specific packets of data are stored in one or more system memory or video memory buffers by an output controller based upon allocation table information. Private data associated with specific elementary streams or packet adaptation fields are repacketized, and written to an output buffer location. In specific implementations, the hardware associated with the system is used to acquire the data stream without any knowledge of the specific protocol of the stream.

Abstract: Symbol timing recovery employs a blind cost criterion from the Bussgang class of functions, and its stochastic gradient, to generate a timing phase error used to adjust sampling of received symbols. For one implementation, the estimate is derived in accordance with the Constant Modulus (CM) criterion and its gradient via the CM algorithm (CMA), and the estimate is calculated from a sequence of samples. This estimate is then used to adjust the period and phase of the sample sequence toward the period and phase of the transmitted symbols, driving the timing phase error to zero. The values used may be either i) samples themselves, ii) processed (e.g., interpolated) samples, or iii) equalized and processed samples. In addition, timing phase error estimates for other cost criteria, including the least mean squares algorithm, may be generated. These timing phase error estimates are selected either alone or in combination for deriving the timing phase error used to adjust the period and phase of the sample sequence.

Abstract: A process and reactor for chemical conversion is taught. The process allows the selective breaking of chemical bonds in a molecule by use of fast rise alternating current or fast rise pulsed direct current, each fast rise portion being selected to have a suitable voltage and frequency to break a selected chemical bond in a molecule. The reactor for carrying out such a process includes a chamber for containing the molecule and a generator for generating and applying the selected fast rise current.

Abstract: Briefly, the present invention includes a method and an apparatus for reducing power consumption in a graphics processing device. The apparatus and method include a memory module monitoring device operative to receive a memory module status signal from memory modules. The memory module monitoring device is operative to generate a clock control signal in response to the memory module status signal. The apparatus and method further include a clock cycle reduction circuit coupled to the monitoring module. The clock cycle reduction circuit receives the clock control signal. The clock cycle reduction circuit generates a reduced cycle clock signal in response to the clock control signal such that the reduced cycle clock signal reduces power consumption in the graphics processing device.

Abstract: A ring oscillator produces an in-phase and quadrature phase radio frequency signal. A first mixer mixes the in-phase signal with a received signal. A second mixer mixes the quadrature phase signal with the received signal. A combiner, operatively coupled to the first and second mixers, produces an image cancelled signal.

Abstract: A computer having an instruction pipeline and profile circuitry. The profile circuitry detects and records, without compiler assistance for execution profiling, profile information describing a sequence of events occurring in the instruction pipeline. The sequence includes every event occurring during a profiled execution interval that matches time-independent selection criteria of events to be profiled. The recording continues until a predetermined stop condition is reached. The profile circuitry detects the occurrence of a predetermined condition, after a non-profiled interval of execution, and then commences the profiled execution interval.

Abstract: A method and apparatus for the display of a viewing events list, wherein a viewing events list includes receiving a plurality of viewing event indicators, wherein each of the plurality of viewing event indicators is associated with event information. The viewing event indicators includes some form of indication of a corresponding underlying viewing event. The method and apparatus further includes prioritizing the viewing event indicators based on the viewing event information and at least one priority rule. The method and apparatus further includes generating the viewing events list including a priority-based listing of the viewing event indicators. Through the association of the priority rules and the corresponding available viewing event indicators, a structured list is provided prioritizing viewing events to assist in a viewer selecting what to watch based on define preferences and priority rules.

Abstract: A method and apparatus for controlling display of content signals begins by receiving a content signal that includes video content and at least one associated content control indicator. The content signal may also include audio content associated with the video content. The processing continues by comparing the at least one associated content control indicator (e.g., a rating of mature subject matter of the content signal) with at least one content control setting (e.g., a parental setting based on allowable viewing of rated content signals). When the associated content indicator compares unfavorably to the content control setting, a video graphics processor scrambles the at least a portion of the video content. The scrambled video content is then provided to a video rendering device for subsequent display.

Abstract: A method and apparatus for graphics processing using state and shader management includes at least one state and shader cache coupled to a compiler for compiling a hardware state and shader vector from an abstract state vector. Also included is an abstract state vector register containing the abstract state vector that is provided to the state and shader cache and the compiler. The state and shader cache receives the abstract state vector and determines whether a cache entry for that abstract state vector already exists. If the cache entry exists, the hardware state and shader vector is provided to hardware. If the entry does not exist, the state and shader cache provides a miss signal to the compiler, whereupon the compiler compiles the abstract state vector and generates a hardware state and shader vector. Thereupon the hardware state and shader vector is provided to the hardware.