Abstract: A method of mapping motion pictures experts group (MPEG) video information for improved efficiency is presented, wherein image information is stored in blocks of memory referred to as tiles. Tiles are mapped in memory so that adjacent tiles only correspond to different banks of memory. A method and system is provided for organizing and routing multiple memory requests from a plurality of clients to multiple memories. Requests from a plurality of clients, including a plurality of clients of the same type, such as multiple MPEG decoders, are directed to different memory controllers by a router. The memory controllers order the client requests by requests among similar client types. The memory controllers also order the client requests by different client types. The ordered requests are then delivered to memory. Returned data is sent back to the clients.

Abstract: A system and method are provided for reducing power consumption within a video processing portion of a system based on display content. Display content is monitored to determine whether the display content is changing. New display content is compared to old display content to determine if the display content is changing. If the display content has not changed, a frame rate used to output display data is reduced. A color depth associated with the display data is also reduced. Power consumption can be reduced when it is determined that display content is not changing.

Abstract: A signal phase shifting circuit shifts the phase of an input signal, such as a STROBE signal, based on a reference signal, such as a CLOCK signal, to facilitate, for example, receiving of double data rate data. The signal phase shifting circuit includes a reference signal period dividing circuit having a feedback delay matching array operatively coupled to one of a plurality of voltage control delay lines. This signal phase shifting circuit also includes a variable delay circuit that provides a phase shifted output signal, such as a phase shifted STROBE signal, that includes a delay stage in a phase shifted output signal drive buffer coupled to the delay stage, such as a voltage control delay line. The feedback delay matching array includes a plurality of serially coupled buffer stages operatively coupled to compensate for delay variations associated with the phase shifted output signal drive buffer in the variable delay circuit.

Abstract: The digital television system that has a zoom module. When the digital television system is in a zoom mode, the zoom module receives a full frame, and displays the zoom frame that includes only a portion of the full frame. The zoom module determines a relationship between the zoom frame and the full frame. The zoom module also identifies an object within a zoom frame, and a motion vector of the object with respect to a background of the zoom frame. As the object moves within the zoom frame, the zoom module adjusts relationship between the zoom frame and the full frame so that the object remains within the zoom frame.

Abstract: A method and apparatus for providing rendering of subsections of screen space receives render commands associated with different screen subsections, such as from a command buffer populated by a coprocessor, and determines which screen section is currently being rendered by a rendering engine, or stated another way, which screen section the host processor wishes to have rendered, and evaluates screen subsection data that is associated with a received rendering command. The screen subsection data identifies a screen subsection for which the command refers. The method includes executing the command if it is determined that the command refers to a current screen section being rendered.

Abstract: A TV signal reception system is configured to include adjustable components and a controller to provide instructions to adjust the adjustable components. By pre-arranging configurations corresponding to multiple variants of world wide TV standards, the TV signal reception system may avoid the hardware costs of accomplishing the reception of multiple standards of with parallel hardware for each standard and/or variant.

Abstract: In a multiprocessor system, a task control processor may be placed in the path connecting each execution processor to a system bus. Such task control processors may detect the completion of a first task on an associated execution processor and, responsively, generate commands to lead to the initiation of a second task on the same, or another, execution processor. Such task completion detection and task initiation by the task control processors removes, from a central processor or the execution processors, the burden of performing such tasks, thereby improving the efficiency of the entire system.

Abstract: A method and apparatus for producing a fragment descriptor for use in oversampling anti-aliasing includes processing that begins by generating a single representative color value for a plurality of subpixels of a pixel. The processing then continues by generating a single representative Z value for the pixel. The processing continues by generating masking information for the pixel, wherein the masking information indicates, for a given object-element being rendered, coverage of the pixel by the object-element. The processing continues by packing the single representative color value, the single representative Z value, and the masking information into a fragment descriptor. The processing continues by transporting the fragment descriptor to a custom memory. When the custom memory receives the fragment descriptor it unpacks it to recapture the single representative color value, the single representative Z value and the masking information.

Abstract: A method and a computer for performance of the method. While executing a program on a computer, profileable events occurring in the instruction pipeline are detected. The instruction pipeline is directed to record profile information describing the profileable events essentially concurrently with the occurrence of the profileable events. The detecting and recording occur under control of hardware of the computer without software intervention.

Abstract: Systems and methods are provided for supporting an external display on a portable device. A system on a chip (SOC) of the portable device provides a first set of graphics data to a graphics controller. The embedded graphics controller renders the first set of graphics data for output using an LCD screen integrated with the portable device. The SOC renders a second set of graphics data and provides rendered graphics data to an external display interface. The external display interface formats the rendered graphics data for output on an external, remote display.

Abstract: A hardware tessellation circuit serves as a unified hardware parametric coordinate generator for providing parametric coordinates for tessellation. The tessellation circuit includes control logic that receives tessellation instruction information, such as an instruction indicating which type of multiple tessellation operations to perform, on an incoming primitive wherein the different types of tessellation include discrete tessellation, continuous tessellation and adaptive tessellation. The tessellation circuit also includes shared tessellation logic that is controlled by the control logic, and includes a plurality of shared logic units, such as arithmetic logic units, that are controllable by the control logic based on the type of tessellation detected to be used for the incoming primitive. The shared tessellation logic is controlled to reuse at least some of the logic units for two different tessellation operations defined by the tessellation type information.

Abstract: An apparatus with circuit redundancy includes a set of parallel arithmetic logic units (ALUs), a redundant parallel ALU, input data shifting logic that is coupled to the set of parallel ALUs and that is operatively coupled to the redundant parallel ALU. The input data shifting logic shifts input data for a defective ALU, in a first direction, to a neighboring ALU in the set. When the neighboring ALU is the last or end ALU in the set, the shifting logic continues to shift the input data for the end ALU that is not defective, to the redundant parallel ALU. The redundant parallel ALU then operates for the defective ALU. Output data shifting logic is coupled to an output of the parallel redundant ALU and all other ALU outputs to shift the output data in a second and opposite direction than the input shifting logic, to realign output of data for continued processing, including for storage or for further processing by other circuitry.

Abstract: A stacked die configuration for use in an IC package includes a first IC die mechanically coupled to a substrate material. Mechanically coupled to the first IC die is an interposer having an aperture adapted to receive a second IC die. Mechanically coupled to the first IC die and fitting within the aperture of the interposer is a second IC die. As a result, both the overall height of the IC package and the length of the bond wires connecting each of the members of the stacked die configuration may be reduced.

Abstract: Briefly, graphics data processing logic includes a plurality of parallel arithmetic logic units (ALUs), such as floating point processors or any other suitable logic, that operate as a vector processor on at least one of pixel data and vertex data (or both) and a programmable storage element that contains data representing which of the plurality of arithmetic logic units are not to receive data for processing. The graphics data processing logic also includes parallel ALU data packing logic that is operatively coupled to the plurality of arithmetic logic processing units and to the programmable storage element to pack data only for the plurality of arithmetic logic units identified by the data in the programmable storage element as being enabled.

Abstract: A water softener employs a vessel, a distributor with a manifold body associated to said vessel and a valve control device. A control unit programs operation of the softener. An actuator unit has a cylinder divided into a first chamber and a second chamber. The actuator unit is adapted to move a spool to define different flow ways, for water. The first chamber communicates directly with a water inlet pipe, and the second chamber communicates with the inlet pipe through a valve and an outlet.

Abstract: A video expansion card makes electrical contact with a mating connector via a mixed signal card edge connector formed on a first edge of the video expansion card. The mixed signal card edge connector includes a plurality of contacts to make electrical contact with the mating connector. The plurality of contacts carries, for example, any combination of two channel audio-in and two channel audio-out signals, two S-video signals, two television signals and two composite video signals, or any other suitable signals. The video expansion card may be coupled to an expansion card bracket in a housing having an aperture adapted to receive the mixed signal card edge connector. The housing may be, for example, a personal computer system chassis or cabinet, a processor-based device or any suitable device. A motherboard card edge connector is formed on a second edge of the video expansion card, and couples the video expansion card to the housing.

Abstract: A single instruction, multiple data (SIMD) processor including a plurality of addressing register sets, used to flexibly calculate effective operand source and destination memory addresses is disclosed. Two or more address generators calculate effective addresses using the register sets. Each register set includes a pointer register, and a scale register. An address generator forms effective addresses from a selected register set's pointer register and scale register; and an offset. For example, the effective memory address may be formed by multiplying the scale value by an offset value and summing the pointer and the scale value multiplied by the offset value.

Abstract: In a specific embodiment of the present invention, a graphics device generates digital output data in response to a known input data. The resulting digital output data has an expected circular redundancy check (CRC) value. The generated digital output data is provided to a digital graphics output port associated with the graphics controller, which is thereby transmitted to a test apparatus over a digital graphics cable. The test apparatus performs an analysis on the received digital graphics data. The analysis results are transmitted back to the graphics device over a serial link of the digital display cable. The graphics device receives the transmitted analysis data, which is subsequently used to determine if the graphics device is operating properly. This determination may be made the graphics device, or by a host system for further analysis.

Abstract: An equalizer for use in a communication receiver includes an infinite impulse response (IIR) feedback filter operated in acquisition and tracking feedback modes on a sample by sample basis to form a hybrid Decision Feedback Equalizer (DFE) architecture. In acquisition mode, soft decision samples from the filtered received signal are input to the IIR filter. In the tracking mode, hard decision samples from a slicer are input to the IIR filter. Acquisition and tracking operating modes are selected in accordance with a set of decision rules on a sample by sample basis based on the quality of the current hard decision. If the current hard decision is low quality, then the soft decision sample (acquisition mode) is used. If the current hard decision is high quality, then the hard decision sample (tracking mode) is used. In such manner, the DFE is operated in a hybrid mode, i.e., using both soft and hard decisions on a sample by sample basis.

Abstract: Method of providing closed captioned data to a television viewer comprised of detecting closed captioned data signals transmitted in conjunction with a television signal, decoding the data signals to caption display signals, and displaying the caption display signals on an auxiliary screen separate from a screen displaying the television signals.