Abstract: A gamma correction circuit comprising circuit apparatus for approximating in linear translation circuits successive nonlinear portions of a gamma correction curve, apparatus for applying an input luminance (Y) signal to the circuit apparatus, and selection apparatus for selecting signals translated by any of the circuit apparatus as a gamma corrected output signal depending on whether the input signal falls within predetermined ranges approximately corresponding to the nonlinear portions of the gamma correction curve.

Abstract: The invention features the generation of timing signals for use in the generation of a video signal. Vertical timing codes and horizontal timing codes are stored in a memory. The horizontal timing codes define regions of at least two types of horizontal timing signals of the video signal, and the vertical timing codes define the timing of the horizontal timing signals. The vertical and horizontal timing codes are stepped through to generate at least one signal indicative of the timing of the horizontal timing signals.

Abstract: A 1:2 or 2:1 audio sampling rate conversion filter converts audio signals from a first sampled rate to a second sampled rate has a multi-coefficient subfilter for receiving a plurality of audio signal samples from buffer memory obtained by sampling at the first sampled rate, and for performing convolution on the plurality of audio signal samples to generate a multi-coefficient based convolution product. In combination with the multicoefficient subfilter, the audio sampling rate conversion filter has a single coefficient subfilter for only receiving a middle sample from the buffer memory and for performing convolution on the middle sample using a single middle coefficient to generate a single middle coefficient based convolution product.

Abstract: A method and apparatus for optimizing digital processing in a computer system is accomplished when at least one of a plurality of digital processing operations (i.e., a set of programming instructions) receives a user request. The user request may include a request to execute the set of programming instructions and may further include data which would be operated upon by the digital processing operation. Upon receiving the request, the addressed digital processing operation (DPO) informs a controlling digital processing operation of the request, such that the controlling DPO may determine whether the addressed digital processing operation is of a first type. A first type digital processing operation is one that may produce a hang-up, an error, or is not optimized when executed alone or when executed in parallel with another digital processing operation.

Abstract: An integrated circuit modeling system facilitates automatic design of register based hardware devices by generating major pieces of the development outputs from a single input, such as a single register specification source file. The modeling code is kept coherent for all major phases of design and testing. The register specification source file contains all the register information about the device being developed. For example, each register defined in the file contains information about its offset (within its register space), access permissions, size, and field specifications. The system uses a series of associated pre-stored modeling templates in different programming languages, that access the register specification source file and automatically generate behavioral model register code and IC simulation code.

Abstract: A method and apparatus for co-processing multi-formatted data which begins when a host processor writes data blocks, in a substantially continuous manner, into memory. Each of the data blocks includes a plurality of data elements and each data element has one of a plurality of data formats. As the data block is being stored in memory, a co-processor retrieves selected data elements from the memory. Upon retrieving the selected data elements, the co-processor interprets them to identify the data format. If the data format is consistent with the data format of the co-processor, the co-processor processes the data element without conversion. If, however, the data format of the selected data element is not consistent with the data format of the co-processor, the co-processor converts the format of the selected data element into the format consistent with the co-processor.

Abstract: A sample rate conversion system and method uses a digital signal processor (DSP) and a separate sample rate conversion circuit (SRC) to perform multiple stream conversion and mixing of different rate input audio streams. The sample rate conversion system converts data, such as multiple streams of digital audio data sampled at different rates, and performs interpolation, decimation, FIR filtering, and mixing of multiple streams of data using the separate SRC. The SRC uses two bidirectional I/O memories for alternately storing input and output data as part of a sample rate converter. When the sample rate converter writes output to one of the bidirectional memories, it has the option of summing the data with the data already stored in the same I/O memory. Therefore a separate digital signal processor can use the sample rate converter circuit to perform some of the mixing for the multiple streams.

Abstract: An automatic volume control system and method for use in a multimedia computer system having at least one speaker and at least one audio generating device accumulates a status of the audio generating device to determine if it is on or off. The system recognizes an audio mute event notification signal from a notification device, such as an incoming telephone call notification signal, and selectively generates a control signal for use in varying the volume to the at least one speaker in response to the detection of the notification signal to selectively control audio from the audio generating device. The system also accommodates multiple audio generating devices. The system analyzes the location of the telephone, speakers and audio generating devices to determine the type of action that is necessary.

Abstract: A method and apparatus for determining visibility of determining a pixel during video rendering is accomplished by determining z-positioning information of an object element. The z-positioning information is representative of the z-information of an object element in a particular section of the display. For example, the z-positioning information may be the two most significant bits of the z-parameter, or information, of an object element. Having determined the z positioning information, a comparison is made between the z positioning information of the object element and z positioning information stored in temporary memory. If this is the first object element being rendered, the z positioning information stored in the temporary memory will be initial z positioning information. When the comparison is favorable, i.e.

Abstract: A method and apparatus for controlling an output frequency of a phase locked loop is accomplished by determining a plurality of divider ratios which are based on an input frequency, parameters, and a desired output frequency. Each of the divider ratios is representative of a ratio between the output frequency and input frequency of the phase locked loop. Having determined the plurality of divider ratios, another determination is subsequently made to determine whether the plurality of divider ratios enable the phase locked loop to produce the output frequency within a given frequency tolerance, i.e., within an allowable error. The determination is based on whether changing the divider ratio from the one of the plurality of ratios to an adjacent ratio causes the output frequency to change more than the allowable error. If so, the plurality of ratios needs to be recalculated based on a change in the input frequency and/or one of the parameters.

Abstract: A sample rate conversion system and method uses a digital signal processor (DSP) and a separate sample rate conversion circuit (SRC) to perform multiple stream conversion and mixing of different rate input audio streams. The sample rate conversion system converts data, such as multiple streams of digital audio data sampled at different rates, and performs interpolation, decimation, FIR filtering, and mixing of multiple streams of data using the separate SRC. The SRC uses two bidirectional I/O memories for alternately storing input and output data as part of a sample rate converter. When the sample rate converter writes output to one of the bidirectional memories, it has the option of summing the data with the data already stored in the same I/O memory. Therefore a separate digital signal processor can use the sample rate converter circuit to perform some of the mixing for the multiple streams.

Abstract: A method and apparatus for providing serial transmission of a parallel input is accomplished by a parallel input serial output transmitter that includes a shift register operably coupled to receive a parallel input and to provide data serially to a gating circuit. The gating circuit, based on the state of the data it receives, generates a drive signal which causes a switching circuit to route current from a first current source to a second current source over different paths to produce a serial output. A bias circuit is coupled to the switching circuit to bias the serial output to a desired level.

Abstract: A method and apparatus for reconfiguring an integrated circuit based on testing results is accomplished by an integrated circuit that includes a first circuit, a second circuit, and configuration circuitry deposited on a single die. After testing of the die, the configuration circuitry configures the integrated circuit based on the results of the testing. If both circuits passed the testing, the configuration circuitry couples, where appropriate, the first and second circuits together. If, however, the first circuit failed the testing and the second circuit passed the testing, the configuration circuitry configures the integrated circuit as if only the second circuit were present on the die. If, however, the second circuit failed the testing and the first circuit passed the testing, the configuration circuitry configures the integrated circuit as if only the first circuit were present on the die.

Abstract: A display FIFO memory management system and method includes a programmable FIFO emulator for emulating a drain and fill time of the display FIFO memory to automatically predict a number of register entries remaining in the display FIFO memory at each predefined clock cycle. A programmable timer/counter has programmable precision to accommodate varying bandwidths of display screen display modes and is used to determine the number of entries remaining so that the emulator can accommodate varying screen display modes. A FIFO controller controls the timing of fetching display data from memory to fill the display FIFO memory based on the prediction of the number of remaining register entries in the display FIFO by the programmable emulator.

Abstract: A method of addressing a computer subsystem memory comprised of establishing an aperture having a predetermined page size, addressing the memory at address boundaries defining multiples of half the page size, and reading or writing a page of data from or to the subsystem memory using the established aperture at consecutive memory locations beginning at one of the boundaries.

Abstract: A display list contains a plurality of entries which each point to a block of data to be displayed on a display screen. An attribute field associated with each entry defines the type of data in the block, so that the data may be properly processed and converted to a displayable image. The display list allows for multiple windows of different data types to be quickly processed and simultaneously displayed on the display screen.

Abstract: A method of converting video data from a YUV format to an RGB format comprising (a) performing a matrix transformation of Y, U and V pixel data of a set of possible Y, U and V parameters into corresponding R, G and B parameters, (b) determining whether the set of R, G and B parameters forms a first lookup table whose size exceeds the size of a particular memory space, (c) in the event the lookup table is too large for the memory space, truncating least significant bits of at least the U and V parameters, (d) repeating steps (a), (b) and (c) until the first lookup table fits the memory space, and then storing the first lookup table in the memory space, and (e) using the first lookup table to provide RGB pixel data using the YUV data as addresses thereto.

Abstract: A method and apparatus for self-testing of a multimedia subsystem is accomplished by retrieving a pattern from a first section of memory, where the retrieving is done by a video graphics circuit. Having retrieved the pattern, the video graphics circuit provides it to a video capture circuit via a television encoder. Upon receiving the pattern, the video capture board generates a capture pattern therefrom. The capture pattern is then provided by the video capture circuit to memory via the video graphics circuit. Once the video capture pattern is stored in memory, the capture pattern is compared with the original pattern. When the comparison is favorable, the video capture circuit, the television tuner, and the interconnecting paths have passed testing.

Abstract: A method of rasterization of a polygon in a 3D draw engine, comprising storing data defining a polygon in a memory organized in pages, the polygon crossing a memory page boundary, comprising rasterizing a first portion of the polygon contained within a memory page, and subsequently rasterizing a second portion of the polygon which is located outside the memory page.

Abstract: A voltage scaling circuit for protecting an input node to a protected circuit uses a voltage shifting circuit that includes two nmos transistors. One nmos transistor is configured as a bi-directional voltage follower and the other nmos transistor is configured as uni-directional voltage follower to facilitate input high level shifting between an input signal node, such as a pin of an integrated circuit and an input node to the protected circuit.