Abstract: A method and apparatus for controlling contrast of images when displayed on a monitor begins when signals corresponding to an image and a contrast feedback signal are received. The signals are mixed with the contrast feedback signal to produce image output signals. The contrast feedback signal is, in turn, determined based on the contrast level of the image output signals. As such, a closed loop feedback circuit is provided to control the contrast levels of the image output signals.

Abstract: A method and apparatus for mapping a linear address to a tiled address that reduces latency between retrieval of pages of data is accomplished when a video graphics processor receives a linear address from the central processing unit and determines whether the linear address is referencing a tiled surface, which is one of up to four portions of the memory. If so, the video graphics processor obtains parameters of the tiled surface. Having obtained the parameters, the video graphics processor determines a normalized linear address based on at least one of the parameters and the linear address. Having done this, the video graphics processor determines a band pointer of the tiled surface based on at least one of the parameters, the normalized linear address and a modular function. In essence, the band pointer points to a normalized initial address of a band of a tiled surface, which includes a plurality of bands.

Abstract: A multiplier is configured to multiply two signed values to generate sum and carry bit groups representing, in redundant form, a product of the first and second signed values. A sign determining circuit is configured generate a sign bit representing a sign of the product. An extension unit is configured to receive the sum most significant bit, the sign bit, and the carry most significant bit. The extension output terminal configured to carry a replacement bit and an extension bit, the replacement bit having a same weight as the sum most significant bit. The extension unit is structured such that the replacement bit has one binary state only if the sum most significant bit and the carry most significant bit are different. The extension unit is structured such that the extension bit has one binary state only if the sign bit is a binary zero and the sum most significant bit and the carry most significant bit are the same.

Abstract: Disclosed is an overload protection device to be placed between a robot and a tool to be used by the robot to prevent damage when the tool encounters an obstacle. The overload protection device comprises a housing, a cam, and a piston. The housing includes an internal cavity and an external opening to the cavity. The cam includes a head portion retained within the cavity and a neck portion extending through the opening. The neck portion and the opening include matching conical surfaces adapted to mate with one another. The piston is disposed within the cavity and tends to urge the cam toward a home position. When the tool is displaced in the x, y, z, or rotational directions during an overload condition, the cam is displaced from the home position. The piston then urges the cam to return to the home position regardless of the direction of displacement. A single sensor is provided to detect an overload condition.

Abstract: A method and system to automatically align overlaying video data on a computer screen based on input information of R or G or B data, horizontal synchronization signal data (Hsync) and vertical synchronization signal data (Vsync) automatically reconstructs a pixel clock time base of an offboard underlying graphics source for use in aligning overlaid video using a generated vertical pixel pattern. The system and method also automatically detects a size of an active computer screen region and position of a top left hand corner and a bottom right hand corner of the active computer screen region to align overlaying video using the reconstructed pixel clock time base and a single color block pattern.

Abstract: A method and apparatus for processing video graphics utilizing less power is accomplished by providing a clock circuit that generates a clock signal. The clock signal is fed to a synchronization circuit that generates horizontal and vertical retrace. The clock signal is also provided to a look-up table DAC (digital to analog converter), or a palette DAC. While the video graphics circuit is processing data for display, the clock circuit provides the clock signal to the both the look-up table DAC and the synchronization circuit. When the data being processed is non-video data (i.e., the horizontal and vertical synchronization information), the clock circuit ceases to provide the clock signal to the look-up table DAC, which disables the look-up table DAC. Thus, it is not consuming power. The clock circuit again provides the clock signal to the look-up table DAC when the data being processed is video data (i.e., the data that is to be displayed).

Abstract: A method and apparatus for tiling a block of image data is accomplished by first receiving a set of parameters that describe the block of image data. An address is determined based on the set of parameters, and the address is translated to a corresponding tiled address. In translation, the address is first separated into horizontal and vertical coordinates. The horizontal coordinates are applied to a horizontal lookup table to obtain a horizontal component of a destination offset, and the vertical coordinates are applied to a vertical lookup table to obtain a vertical component. The horizontal and vertical components are then combined to produce the destination offset. The destination offset is added to a destination base pointer to produce the corresponding tiled address. Data is copied from the address to the corresponding tiled address. The address is then incremented, and the process is repeated for each address in the block of image data.

Abstract: A method for producing a modified cursor in a video graphics display system is accomplished by receiving data corresponding to the modified cursor and comparing the received data with cached cursor information. If the comparison produces a favorable result, a pointer is stored in a cursor offset register, where the pointer corresponds to a data set in video memory that describes the modified cursor in a video format. When the comparison produces an unfavorable result, a video format data set is generated for the modified cursor and is stored in the video memory. A pointer to the new video format data set is stored in the cursor offset register, and at least a portion of the received data is stored with the cached cursor information.

Abstract: A variable length fractional bandwidth low-pass filter is implemented as a plurality of filter stages. Each filter stage performs fractional filtering of a plurality of input samples to form an output sample. The number of filter stages is determined based on the characteristic of the filter stage, and the load is suitably balanced to allow for a minimal number of filter stages. Load balancing is applied so as to utilize each of the filter stages only when required. The load balancing is applied so as to provide a substantially equal load to each filter stage, and the number of filter stages is determined so as to allow the filter to operate substantially at the input sample rate.

Abstract: An image reconstruction system adaptively de-interlaces video stream content using image data comparison techniques when the interlaced input video stream does not contain pre-coded non-interlaced to interlaced conversion status data. In one embodiment, the system uses a signature generator which generates a plurality of field signature values on a per field basis by determining region values based on fluctuations in pixel data, such as luminance data within a horizontal scan line to detect changes in motion. The field signature values are then analyzed to determine a probability that the content is one of several types such as content that has undergone non-interlaced to interlaced conversion, such as pull down conversion for film captured content. Also, independent of whether conversion has occurred, the system analyzes the video streams to determine whether the video stream contains a paused image or slow motion playback of images and de-interlaces accordingly.

Abstract: An adaptive audio signal compression computer system corrects multiple input audio streams, such as digital multichannel audio streams from various audio sources, for equalization deficiencies caused primarily by attenuation factors experienced by a listener's human ear. A compression stage (filter stage) adaptively compresses (filters) an input audio stream by selecting the ear response data that includes a plurality of selectable sets of filter coefficients wherein each set of filter coefficients corresponds to an inverse audible listening response curve for a predetermined audio volume level. When available from an audio source, the system provides audio source type data to an adaptive compression stage and also generates a compression control signal in response to the source type data to control the compression.

Abstract: A method and apparatus for rendering pixel information from blended texture information is accomplished by generating first texture information and second texture information for a given pixel location. Having generated this information, the first and second texture information is blended, based on a blending function, to produce blended texture information. The blended texture information is then used to render the pixel information at the given pixel location. This process continues for each pixel location of an object element of an object, image, and/or scene.

Abstract: A method and apparatus for space variant texture filtering begins when texture coordinates for a given pixel of an object being rendered are received. From the texture coordinates, first and second axis derivatives are determined. When the first and second axis derivatives have differing degrees of magnitude, a determination is made as to whether the first access derivative or the second axis derivative corresponds to a major axis. Next, a number of samples along the major axis are determined based on a logarithmic function of a ratio between the first and second derivatives. Having obtained the number of samples, a separation between the samples is determined based on derivatives along the major axis. Having obtained the number of samples and separation, one of a plurality of related texture maps (e.g., MIP maps) is referenced based on the derivatives along a minor access to obtain the samples.

Abstract: A method and apparatus for testing specific assembled circuits begins by configuring a plurality of applications specific testing entities to test assembled circuits, where the configuring is based on the types of assembled circuits being tested. Next, a specific assembled circuit testing program is provided to the corresponding application specific testing entity based on the type of assembled circuits it is testing. In addition to providing the testing programs to the testing entities, programming instructions are provided to a programmable handler to pick and place the appropriate assembled circuits with the corresponding applications specific testing entities. When the testing of a particular assembled circuit is complete, a test complete indication is provided.

Abstract: A method and apparatus is used in a graphics system to scan a polygon that minimizes the number of pixels scanned outside of the polygon. A direction (e.g., the direction of the major scan axis) is chosen so that once inside the polygon, advancements along the direction do not take the scanning outside of the polygon until substantially all of the interior pixels of the polygon have been scanned. The direction is selected based on the angular orientations of the edges of the polygon. During the scanning, advancements along the direction result in starting points from which lines are pixels are scanned (e.g., lines following a minor scan axis). Each line of pixels ends at one of the edges of the polygon.

Abstract: A method and apparatus for detecting differences between an image update rate and a display update rate and to provide a viable solution that produces minimal adverse visual effects is achieved by first detecting an image delineation from a stream of images. The image delineation is then used to determine the image update rate which is compared to the display update rate to produce a relationship between the two update rates. The relationship is then compared to a plurality of desired relationships to determine if it is sufficiently similar to one or more of the desired relationships. If it is, an image display pattern associated with the desired relationship is used. For example, if the relationship is sufficiently similar to the desired relationship of 1:1, then the image display pattern will be 1111 . . . In other words, the image display pattern would display each received image once.

Abstract: A method and apparatus for emulating operation of a complex circuit within a system, thereby creating a virtual system, is achieved within a system that includes a central processing unit (CPU), system memory, at least one functional module, and an emulator that includes a circuit simulator, a virtual coupler, and an evaluation module. The circuit simulator simulates the functionality of the complex circuit, includes an individual system identifier, and is operably coupled to, and substantially controlled by, the at least one functional module. At system start-up, or at initiation of a simulation test, the system determines its configuration by obtaining the individual system identifiers of each system element. Because the circuit simulator has a system identifier, it is treated by the system as a real entity. As such, when the CPU requests the function of the complex circuit to be performed, the CPU provides its request to the at least one functional module.

Abstract: A horizontal phase detection circuit and system detects the phase of the horizontal synchronization pulse for a horizontal synchronization phase lock loop using positive and negative fractional error compensation. The positive and negative fractional errors are determined to get a more accurate detection of where a horizontal synchronization pulse crosses a synchronization signal slice level. Using both positive and negative fractional compensation, the circuit and method detects the horizontal synchronization pulse width and center of the pulse. In addition, if desired, an adaptive slice level generator generates a variable slice level threshold based on a signal strength of the input video signal to facilitate improved detection in the cases where the video information is weak even after gain control has been applied.

Abstract: An audio bus interface system and method interfaces a plurality of digital signal processing devices to an audio bus to facilitate variable processing loading on the DSPs. The audio bus contains frames with synchronization data. The system utilizes a programmable interrupt controller for each digital signal processing unit. The programmable interrupt controller controls the rate at which a given DSP can be interrupted. The respective digital signal processor controls the programmable interrupt controller to maximize its throughput. Also, an audio format translator allows differing audio format protocols to be processed by the same audio DSP.

Abstract: A method and apparatus for memory allocation in a multi-processor system is accomplished by mapping portions of a shared memory to a first and second processor. The mapping is performed such that either of the processors' portions can be enlarged or reduced based on the memory that is located between the portions allocated to the processors. When a processor requests additional memory and there is sufficient free memory between the processors' respective portions, the appropriate amount of the free memory is allocated to the requesting processor.