Abstract: An integrated circuit and method utilizes a differential input receiver having a first input that receives an input signal. A reference voltage adjustment circuit produces a variable reference signal for the second input of a differential input receiver. A feedback path is provided from the output of the differential input receiver to an input of the reference voltage adjustment circuit. The reference voltage adjustment circuit dynamically varies the variable reference voltage signal to facilitate hysteresis. The variable reference voltage signal is lowered in the case of a high input signal, and raised in the case of a low input signal.

Abstract: A buffer circuit utilizes a single gate oxide pre-buffer voltage level shifting circuit on, for example, an output buffer of an I/O pad, to accommodate different I/O pad supply voltages while maintaining normal operating voltages (degradation levels) across boundaries of single gate oxide devices that form the buffer. The single gate oxide output buffer can operate at several different supply voltages. A pre-buffer voltage level shifting circuit includes a multi-supply voltage level shifting circuit having single gate oxide devices coupled to produce a pre-buffer output signal to an output buffer. A single gate oxide cross coupled active load is coupled to the multi-supply voltage level shifting circuit and provides suitable drive voltages to at least one of cascaded buffer transistors.

Abstract: In accordance with the present invention, an adder tree structure includes at least two adder stages. In the circuit and method according to the present invention, the first of the two adder stages generates two bits of a common weight and other more significant bits of a weight one bit more significant than the two bits of the common weight. The second of the two adder stages includes an adder that receives the more significant bits generated in the first of the two adder stages. The second adder stage also includes an AND gate which receives and logically AND's the two bits of the common weight to generate a carry-in bit for the adder in the second stage. The above adder tree structure and adding method have an advantage of permitting more input terminals of adders to contain information about the input values to the adder tree structure. Therefore, the adders are used more efficiently and less adders are required to perform a specific function.

Abstract: A signal representation method and apparatus for digital audio provides high quality low cost resampling by transferring the difficult interpolative computations into front-end (off-line) preprocessing, thereby reducing the load on the tone generating synthesis processor. This allows nearly perfect arbitrary-ratio resampling of stored waveforms at a fraction of the cost of prior art resampling. It also allows elimination of the prior art polyphase coefficient table since the waveform reconstruction information is fully contained within the polynomials. This is especially advantageous for execution on general purpose multi-tasking media processors.

Abstract: The invention features furnishing a representation of the quadrature amplitude modulation of two input signals (e.g., U and V video signals) based on the phase of a reference signal (e.g., a color burst reference signal). The two input signals are scaled based on the phase of the reference signal, and the scaling is synchronized to the phase of the reference signal.

Abstract: A method and apparatus for a processing system to utilize a ring buffer includes a host processor, memory, and at least one co-processor. The host processor generates a plurality of data blocks that relates to a particular application (e.g., word processing application, drafting application, presentation application, spreadsheet application, video game application, etc.). The host processor writes data elements of the data blocks into the memory, which is organized in a ring buffer manner. As the host processor enters the data elements into the ring buffer, it updates a head pointer, which indicates the most current address of a data element entered into the ring buffer, in its local cache. The co-processor retrieves the data elements from the ring buffer and performs a co-processor function in support of the particular application.

Abstract: A method and apparatus for scaling graphics data is begins by retrieving a line segment of graphics data from a frame buffer, or memory, which stores the graphics data in lines. Once the line segment of a current line has been retrieved, a corresponding line segment of another line is retrieved from a line buffer. The two line segments are then blended together to produce blended pixel information. The blended pixel information is then scaled and subsequently stored to produce a resulting graphics output. After the corresponding line segment has been retrieved from the line buffer, it is overwritten with the currently retrieved line segment.

Abstract: Disclosed are male and female electrical contacts for transferring high electrical power between a master assembly and a tool assembly of a robotic tool changer. The male and female contacts have corresponding outwardly-projecting and inwardly recessed conical or frusto-conical contact surfaces which tend to cause contaminants to slide off the surface of the contacts. The contacts may instead have corresponding outwardly-projecting and inwardly recessed contact surfaces having spherical, frusto-spherical, ellipsoid, frusto-ellipsoid, ovoid, or frusto-ovoid shapes. Each of the contacts includes a contact base for attaching the contact to one of the assemblies of the robotic tool changer and a contact tip removably attached to the contact base, thereby allowing the contact tip to be replaced without detaching the contact base from the robotic tool changer. The contact tip of either or both of the electrical contacts is mounted in such a way as to have compliance in at least one direction.

Abstract: A method and apparatus that allows a user to preview live audio and/or video of a channel displayed in a multiple channel selection display prior to making a complete selection is generally accomplished by providing pixel information for displaying visual representations of a plurality of channels where the video representation of each channel is displayed in a corresponding channel display area (i.e., a video thumbnail). When the user selects one of the video representations in a preview mode, the video thumbnail is switched from a still image with no audio to an image that includes live audio and/or video. This preview mode remains until the user deselects the preview mode, selects full display area viewing, or a time-out period expires. In addition to the preview option, the user is provided with an editing option that allows the user to customize his or her multiple channel display.

Abstract: A low common mode impedance differential driver includes an independent current source, a switching module, a dependent current source, and a bias control circuit. The independent and dependent current sources are operably coupled to the switching module to provide first and second current paths through the switching module. The bias control circuit is operably coupled to the dependent current source and to the differential output produced by the switching module. The bias control circuit provides a control signal to the dependent current source that causes the common mode of the differential output to be maintained within a desired tolerance.

Abstract: A cache memory system which minimizes the latency and latency uncertainty of data memory access by allocating spare cache memories to subsequent conflicting requests, and maintaining the prior requests in a separate table until the prior request is satisfied and the prior allocated cache is free. This reallocation of physical caches to conflicting requests is effected by maintaining an index to the physical cache that is separate and distinct from the logical index associated with the requests that cause the conflict. A conventional indexed cache mechanism is employed to derive the logical index from a subset of the address of the requested data. When the same logical index occurs from data requests from different blocks of memory, the conflict is resolved by assigning a free physical cache to the latter request. The latter assignment is stored in the indexed cache table, and the former assignment is stored in a separate table until it is no longer required.

Abstract: A system and method for compensating against false color from composite video source information detects when there is a diagonal luminance transition (or a cross pattern) and attenuates combed chrominance information to facilitate a reduction in a false coloring effect. A programmable threshold diagonal transition detector generates a multi-level compensation control signal, such as the amount of chrominance reduction or attenuation (in dB) to effectively notch combed chrominance data, based on a detection of a diagonal transition of luminance data among lines of video data. The multi-level compensation control signal is used by a multi-level compensator to attenuate the combed chrominance information from the 2-D adaptive comb filter.

Abstract: A method and apparatus for providing video graphics processing that includes anti-aliasing begins when a video graphics processor receives vertex parameters of an object-element and walks a first edge of the object element and a second edge of the object element. The video graphics processor walks the first and second edges based on calculations involving a decision corner and an error turn. The calculations indicate which direction to walk on a pixel by pixel basis, i.e., whether the walking should be in the major direction or the minor direction. The calculations also identify pixels that contain fragment pixel information, i.e., the pixels along the edges of the object element. For each fragment pixel, subpixel masks are created for each object element that is present in the fragmented pixel. From the subpixel masks, subpixel sequences are determined, which are used to produce pixel information of the fragment pixel.

Abstract: A method and apparatus for improved double buffering within a computing system begins when a series of data blocks are received from a central processing unit at a rate independent of a processing rate of a recipient engine. For example, a video graphics circuit receives a series of data blocks representing video frames from the central processing unit at a rate independent of the refresh rate of the display. As the data blocks are received, the video graphics circuit queues commands of the data blocks. Typically, the commands include processing commands and a processing rate synchronize command. To process the data blocks, the co-processor pulls commands from the queued list and processes them to produce recipient data. As the co-processor is producing the recipient data, it is utilizing a first buffer. The co-processor continues to process the commands and storing the results into the first buffer until the processing rate synchronize command is detected.

Abstract: A method and apparatus for anti-aliasing a rendered scene begins processing by rendering a plurality of objects of an image to a buffer to produce a rendered image. For example, the image corresponds to a particular frame of data to be displayed on a computer monitor, television, etc. Each of the objects corresponds to portions of the image and is comprised of object-elements (e.g., triangles). While the plurality of objects is being rendered, edge information of the objects that are in a most foreground position is maintained. The edge information includes a pixel offset value, which indicates the offset of an edge from a pixel center, and gradient information of the object edge. After the image has been rendered and the edge information has been collected for a particular frame of data, the rendered image is filtered based on the edge information. In particular, a two-dimensional spatial filter that derives its filtering parameters from the edge information is applied to the rendered image.

Abstract: A method and apparatus for deferred rendering of pixel information is accomplished by receiving at least a portion of an object element list (Eg. triangle descriptor list) which contains object element descriptor information for each object to be displayed on at least a portion of the display. Upon receiving this information, z-components of each object element (Eg. triangle) is compared with the other object elements based on pixel location. As the comparisons are being made, the identity of an object element that is visible at a particular pixel location (Eg. in the foreground with respect to other objects) is stored in a manner that corresponds with the particular pixel location. Once the z-components for all of the object elements have been compared, the object elements identified in the memory have pixel information generated therefor.

Abstract: A multiplier has two input value terminals which receive two signed input bit groups. The multiplier also has two output terminals configured to carry a sum and carry bit group representing, in redundant form, a product of the two signed input values. A sign determining circuit generates a sign bit representing a sign of the product of the two input signed values. An extension unit has three input terminals configured to receive the most significant bit of the sum bit group, the most significant bit of the carry bit group, and the sign bit generated by the sign determining circuit. The extension unit is structure to generate a least significant extension bit and a more significant extension bit. The least significant extension bit has one binary state if the sum most significant bit, the sign bit, and the carry most significant bit have the same binary state. The least significant extension bit otherwise has the opposite binary state.

Abstract: A method and apparatus for determining the level of detail for texture mapping applications in video graphic circuits begins by updating first and second linear components of a set of derivatives when rendering a pixel of an object in a given scan line. The first and second linear components are updated in a linear manner based on first and second increment values, respectively. The set of derivatives corresponds the changes of the texture coordinates with the changes of the physical coordinates of an object being rendered, the derivatives include .delta.s/.delta.x, .delta.t/.delta.x, .delta.s/.delta.y, and .delta.t/.delta.y--in general, the set of derivatives equals .delta.a/.delta.b=w.sup.2 *((1/w)*(.delta.(a/w)/.delta.b-(a/w)*(.delta.(1/w)/.delta.b))). When the object is being rendered on a new scan line, third and fourth linear components are updated in a linear manner based on third and fourth increment values, respectively.

Abstract: The invention features a method and apparatus for use with a computer system having a memory and a bus (e.g., a PCI bus). The bus is monitored for detection of a bus cycle intended for a controller (e.g., a DMA controller) used to transfer data between a bus device and the memory. After detection, the bus device is used to claim the bus cycle and to emulate the response of the controller to the bus cycle.