Abstract: Initializing and configuring computer hardware with firmware stored in compressed form in nonvolatile semiconductor memory. Upon startup of the computer hardware, decompression software decompress the firmware, which is then stored in another memory. The computer hardware may be an adapter board (e.g., a graphics board connected to PCI bus), the nonvolatile semiconductor memory may be physically located on the adapter board, and the firmware may be firmware for initializing and configuring the adapter board. The decompression software may be stored in the same nonvolatile semiconductor memory as the firmware, and may be written in a machine-independent language (e.g., a Forth-based language). The compression technique used may include both run-length encoding and pattern compression, and may operate at the bit level.

Abstract: A method and apparatus that automatically scales the channel display area (i.e., thumbnails of the channels) based on the number of channels and displaying characteristics and that provides the user with options to customize the plurality of channels displayed in the multi-channel display is accomplished by determining whether all of the channels in the user's customized list can be displayed within the given display area, which may be the full screen or a portion thereof. If all of the channels can be displayed in the given display area, another determination is made to determine the size of each of channel display areas (i.e., thumbnail). Having made this determination, visual representations of each channel in the user's customized list is displayed. While the multi-channel display is being presented, the user can select one of them for customized editing.

Abstract: A system, and corresponding method for its use, for performing various monetary transactions in a vehicle such as an aircraft, including exchanging one currency for another, obtaining currency using traveler's checks or a credit or debit card, and dispensing value cards purchased with cash or credit/debit cards. The value cards may be, for example, long-distance telephone usage cards or gaming cards, and the value cards may be increased in value or exchanged for cash using the system of the invention. A key feature of the system is that cash is always distributed in the currency of the next destination of the aircraft, as determined from flight management system data available on the aircraft. At each intermediate destination, a note dispenser is conditioned to dispense only the currency of the next destination.

Abstract: A material aerating and mixing machine having a material elevator which elevates, mixes and aerates the material to be processed. The material from the elevator is discharged onto a pair of conveyors, a cross conveyor that can be side shifted for windrow turning, and a discharge conveyor that is pivotally mounted for swingable movement in a horizontal plane into a different positions, one position being in line with the cross conveyor for truck loading, another at an angle for stack turning, and a third position where the conveyor is folded for windrow turning or transport. Each of the conveyors is independently powered depending upon the mode in which the machine is operated.

Abstract: A rasterizer is used with a system capable of furnishing raster data representative of a string of characters to be formed on a display. The rasterizer has an input interface that is connected to receive the raster data from the system. A graphics engine is connected to use the raster data to simultaneously store representations of portions of at least two of the characters in a memory. An output interface is connected to use the representations stored in the memory to form an output signal which is used by the display to form the characters.

Abstract: A method and apparatus for providing interlaced video data on a progressive display is accomplished upon receiving interlaced image data that is temporally and spatially accurate and calculating, based on a first predetermined function, calculated image data. Next, the calculated image data is compared to a threshold. When the calculated image data exceeds the threshold, the received interlaced image data is adjusted to approximate the threshold. When the calculated image data does not exceed the threshold, the received interlaced image data is adjusted to equal the calculated interlaced data. Having done this, additional information is created and subsequently combined with the adjusted interlaced image data to produce a complete field for display on the progressive display. The additional image information is of a first value when the calculated image data does not exceed the threshold and is as functional value when the calculated image data exceeds the threshold.

Abstract: A method and apparatus for generating a finely adjustable clock is accomplished by a ring oscillator, a plurality of counting circuits, and a controller. The ring oscillator generates a plurality of oscillations, wherein each of the oscillations have an approximately equal period and are phase shifted by an approximately equal phase shift. Each of the plurality of oscillations is provided to one of the counting circuits which divides the frequency of the respective oscillation by a given count value to produce corresponding periodic representation. The controller selects one of the corresponding periodic representations based on control signal to be the output oscillation, or clock signal. When the clock signal needs to be finely adjusted, the controller, based on the control signal, selects another one of the corresponding periodic representations.

Abstract: A method of reconstructing a stream of digital frequency domain audio signal samples into audio signals comprising parsing the stream of samples and reconstructing subband data in the frequency domain, processing the subband data to obtain a processed frequency domain digital audio signal, and constructing a time domain audio output signal from the processed frequency domain digital audio signal.

Abstract: A voltage controlled oscillator comprising: a ring of inverters comprised of an odd number of serially connected CMOS inverter stages, the inverter stages being connected between first and second oppositely poled power leads, a MOSFET having a source-drain circuit connected between one of the power leads and a first power rail, the other power lead being connected to a second power rail, apparatus for operating the MOSFET in saturation, and apparatus for applying a control voltage to the gate of the MOSFET, referenced to the second power lead, whereby the MOSFET operates as a nonlinear current conduction device having a characteristic such as to linearize the voltage-frequency characteristic of the combined MOSFET--ring oscillator combination.

Abstract: A charge pump comprising a first branch PMOS FET having a source connected to a voltage source and a drain connected to an output node, a second branch NMOS FET having a drain connected to the output node and a source connected to a ground node, first apparatus for selectively switching a gate of the PMOS FET between its source and a first bias voltage source, and second apparatus for selectively switching a gate of the NMOS FET between its source and a second bias voltage source, the bias voltages being of magnitudes such that the first branch PMOS FET and second branch NMOS FET will source and sink the same magnitude of current when the FETs are fully conducting.

Abstract: A programmable frequency synthesizer comprised of a phase locked loop (PLL) including a current controlled oscillator (ICO), a level translator for receiving output signals from the ICO wherein the output signals have a finite slew rate, a reference source of signals, a phase-frequency detector for receiving signals from the reference source and output signals generated by the level translator and for providing pulse signals to the ICO having pulse widths which are directly proportional to phase difference between the signals from the reference source and the output signals from the level translator, and apparatus for varying the slew rate of the output signals from the ICO wherein the duty cycle and thus the frequency of output signals of the level translator may be varied.

Abstract: A method of scan conversion comprising (a) receiving source data representing a predetermined signal component of respective pixels of successive lines of a non-interlaced display, (b) adding the source data related to vertically adjacent pixels in a set of source lines of the non-interlaced display to form one of an odd and even line of an interlaced display, (c) repeating step (b) for another immediately following set of source lines to form another one of the odd or even line of the interlaced display, and (d) repeating steps (a), (b) and (c) successively to an end of an odd or even field of the interlaced display.

Abstract: A method of controlling the display of graphics data on a computer display, the computer comprising a draw engine, comprised of detecting predetermined logical condition of a draw operation for display, saving the state of the draw engine, performing a new draw operation, and restoring the state of the draw engine.

Abstract: A method of performing a bit block transfer (Bitblt) comprised of reading a pixel data sequence from a source trajectory, writing an X coordinate portion of the pixel data sequence to a destination trajectory, repeating the writing step to the end of a scan line in the event the X coordinate portion is smaller than the scan line, reset the X coordinate following the end of the scan line, reset a Y coordinate and write a successive X coordinate portion of the pixel data sequence to the destination register from an X coordinate start position when the Y coordinate actually advances in the pixel data sequence.

Abstract: A computer system is comprised of at least one of a main bus and an attached expansion bus, a CPU connected to the main bus, peripherals connected to one of the main bus or to the expansion buses, a subsystem connected to a bus for receiving control, address and data signals from the CPU comprising a graphics controller, a data compression circuit, a video controller, a memory connected to data input ports of the circuits and controllers via a subsystem bus having a bandwidth sufficient to carry video and graphics display signals, a first arbiter for determining which controller is permitted access the memory, a link bus connecting each of the controllers, and apparatus for providing polling signals to each of the controllers and circuits on the link bus and for receiving acknowledgement signals therefrom, and thereby synchronizing and allowing exchange of control information between the controllers and circuits.

Abstract: The present invention relates to a video display processor comprised apparatus for receiving digital input signal components of a signal to be displayed, apparatus for converting the components to a desired format, apparatus for scaling and blending the signals in the desired format, apparatus for outputting the scaled and blended signals for display or further processing, and an arbiter and local timing apparatus for controlling the apparatus substantially independently of a host CPU.

Abstract: A method of processing audio signals is comprised of reading samples of digitally stored audio signals from a first source memory, performing a bit block transfer (BitBLT) of the samples to a register of an arithmetic and logic unit (ALU), reading an array of coefficient signals (coefficients), performing a BitBLT of the coefficients to a register of the ALU, operating on the bit block transferred samples and coefficients together and storing resulting samples in a destination memory, whereby the stored resulting samples can be further accessed for audio reproduction, further processing, permanent storage or transmission.

Abstract: The present invention relates to an image scaler comprised of apparatus for receiving coefficients a and b and image display values of adjacent pixels P and Q respective of an image, apparatus for repeatedly operating on the coefficients and values for successive pixels according to the transform ##EQU1## where SUM is the sum of the coefficients,R is either zero or the accumulated SUM of an immediately preceding operation,A.sub.cc is an accumulated result signal, and apparatus for providing a first result signal as an output coefficient word for controlling the display of each of adjacent pixels.

Abstract: A method of drawing moving images on a graphics display comprising (a) receiving data defining an input image in a predetermined resolution, (b) commanding a graphics processor to draw a corresponding image frame on a display having a number of scanning lines which is a multiple m of a number of scanning lines of the input image and a multiple n of a number of pixels in a horizontal line of the input image, (c) drawing successive lines of the input image on a first and on each m.sup.th scanning line of the graphics display, while stretching each pixel on each drawn line over n pixels, (d) copying each drawn line on respective immediately following m-1 lines, and (e) repeating steps (b)-(d) for successive frames of the input image.

Abstract: A method of linking peripheral devices to a single interrupt procedure in a computer is comprised of storing in an interrupt vector table of a BIOS ROM, a first pointer to an interrupt service routine related to one of a group of peripheral devices which use the same interrupt request (IRQ) on the same software interrupt vector, and storing further pointer in each one of the peripheral devices to another unique one of the peripheral devices in the group.