Abstract: A baseband processing module for use within a Radio Frequency (RF) transceiver includes a downlink/uplink interface, TX processing components, a processor, memory, RX processing components, and a turbo decoding module. The RX processing components receive a baseband RX signal from the RF front end, produce a set of IR samples from the baseband RX signal, and transfer the set of IR samples to the memory. The turbo decoding module receives at least one set of IR samples from the memory, forms a turbo code word from the at least one set of IR samples, turbo decodes the turbo code word to produce inbound data, and outputs the inbound data to the downlink/uplink interface. The turbo decoding module performs metric normalization based upon a chosen metric, performs de-rate matching, performs error detection operations, and extracts information from a MAC packet that it produces.

Abstract: An BTSC encoder with an improved digital filter structure substantially implemented on a single CMOS integrated circuit is described. By cascading first and second order allpass filter structures to form a higher order digital filter, such as a Cauer low pass filter, limit cycle oscillations are reduced or eliminated, word-length growth from one stage to the next is contained, and a more efficient overall filter structure and performance is obtained.

Abstract: A method and apparatus for communicating information between networked devices. Various aspects of the present invention may comprise, for example, a first networked device communicating information over a wireless communication network to a second networked device having power-save mode capability. The first networked device receives an incoming message from the second networked device. A first outgoing message is transmitted to the second networked device prior to transmitting a previously queued outgoing message. A second outgoing message is transmitted to the second networked device prior to the previously queued outgoing message being transmitted. Information may be communicated to the second networked device in a particular manner that depends on whether the second networked device has power-save capability. Communication medium access may be performed in a particular manner, depending on whether the second networked device has power-save capability.

Abstract: A system and method for Bluetooth® decoding is disclosed and may include calculating a remainder value based on a received bit sequence and a generator polynomial for a corresponding transmitted Bluetooth bit sequence. Remainders may be generated from known error vectors and the generator polynomial. The generated remainders may result in at least a portion of the known error vectors corresponding to the generator polynomial. A codeword may be selected that may correspond to the calculated reminder value that matches one of the generated remainders. The generated remainders may be stored in a look-up table. An initial metric value may be calculated utilizing the following equation: M 0 = ? n = 0 14 ? ? abs ? ( RX ? ( n ) ) , where RX(n) may include the received bit sequence. The codeword with a metric value equal to M0 may be selected, if the calculated remainder value is equal to 0.

Abstract: A dual purpose serializer/de-serializer (SerDes) for point-to-point and point-to-multipoint communication. A configurable SerDes can be designed to operate in one of a plurality of operating modes. Selection between the plurality of operating modes can be based on information received via a management interface. In one example, the various operating modes can be defined with different locking times and jitter characteristics.

Abstract: The present invention relates to a system and method for increasing the manufacturing yield of a plurality of memory cells used in cell arrays. A programmable fuse, having both hardware and software elements, is used with the plurality of memory cells to indicate that at least one memory cell is unusable and should be shifted out of operation. The software programmable element includes a programmable register adapted to shift in an appropriate value indicating that at least one of the memory cells is flawed. The hardware element includes a fuse gated with the programmable register. Shifting is indicated either by software programmable fuse or hard fuse. Soft fuse registers may be chained together forming a shift register.

Abstract: A transceiver for combining RFID amplitude-modulated data with wireless phase-modulated data is realized by a processing module operably coupled to generate outbound non-amplitude modulated symbols from first outbound data, to generate outbound amplitude modulated symbols from second outbound data, to generate first inbound data from inbound non-amplitude modulated symbols, and to generate second inbound data from inbound amplitude modulated symbols, a combiner operably coupled to modulate the amplitude modulated symbols onto a signal carrying the non-amplitude modulated symbols to produce a combined outbound RF signal and a splitter operably coupled to convert a combined inbound RF signal into inbound non-amplitude modulated symbols and into inbound amplitude modulated symbols.

Abstract: A system and method for providing quality-of-service based network resource allocation and utilization in a dynamic network environment. For example, a wireless communication network may comprise a first system and a second system. The first system may provide a current service to a user at a current quality level. The first system and second system may establish a wireless communication link. At least one of the first and second systems may determine whether utilizing one or more resources of the second system will provide the current service to the user at a higher level of quality than the current quality level. One or more resources of the second system may be allocated for providing the current service to a user at a higher quality level. The allocated resources may be utilized to provide the current service to the user at a higher quality level than the current quality level.

Abstract: A system (e.g., a chip) includes first and second function blocks (e.g., function blocks) coupled to an input/output (I/O) device (e.g., a bi-directional pin or pad) via a multiplexing module. The multiplexing module can be used for both input and output of signals between the function blocks and the I/O device. Optionally, a re-clocking system is coupled to the function blocks, the I/O device, and the multiplexing module. The re-clocking system re-clocks one or more signals being input into the multiplexing module so that they are timed correctly for input or output from the system.

Abstract: A multi-port SERDES transceiver includes multiple parallel and serial ports, and the flexibility to connect any one of the parallel or serial ports to another parallel or serial port. The ports include programmable pads that are capable of supporting multiple different data protocols, timing protocols, electrical specifications, and input-output functions. A management data IO pad also enables the transceiver to support different electrical requirements and data protocols at the same time. The substrate layout of the transceiver is configured so that the parallel ports and the serial ports are on the outer perimeter. A logic core is at the center, where the logic core operates the serial and parallel data ports, and the bus that connects the data ports. The bus can be described as a “ring” structure (or donut “structure”) around the logic core, and is configured between the logic core and the data ports.

Abstract: A receiver and receiver front end having multiple independent differential inputs, multiple independent differential low-noise amplifiers, and two sets of double-balanced IQ mixers. The double-balanced mixers include cross-coupled PMOS devices that dynamically inject current at zero-crossing points to cancel out tail currents in the mixers. Also, methods of operating the above-discussed receiver and receiver front end.

Abstract: A wireless human interface device (HID) includes an input interface module for accepting inputs from a user; a microprocessor for processing the accepted inputs; a wireless transmitter for transmitting the accepted inputs to a host; and a temperature sensor for determining the temperature of the wireless HID, wherein the microprocessor transmits the sensed temperature via the wireless transmitter to the host for displaying.

Abstract: Controlling an encryption/decryption device using descriptors may include formatting a first block of memory to contain a generic data template used to control the encryption/decryption device. The first memory block may be configured with actual data values corresponding to the generic data template. At least a portion of the configured actual data values may be acquired and used for controlling one or more operations of the encryption/decryption device. A second memory block may be configured in a manner compatible with the first memory block format. The second memory block may also be configured with actual data values corresponding to the generic data template of first block of memory. The second block of memory may be linked to the first memory block. The first and second block of memory may be a random access memory.

Abstract: A wireless transceiver includes a plurality of antennas. A transmitter section generates a plurality of transmit signals to the plurality of antennas, wherein each of the plurality of transmit signals corresponds to one of the plurality of antennas. A receiver section includes a plurality of low noise amplifier modules generate a plurality of received signals from the plurality of antennas, wherein each of the plurality of received signals corresponds to one of the plurality of antennas and wherein each of the plurality of low noise amplifier modules includes a notch filter for blocking a corresponding one of the plurality of transmit signals. A down conversion module down converts the plurality of received signals to generate a plurality of down converted signals. A recombination module generates an inbound symbol stream from the plurality of down converted signals.

Abstract: A mobile communications device includes one or more antennas and a plurality of wireless transceivers that are each configured to transmit and receive transmissions via the one or more antennas according to at least one of several associated communications protocols. The device includes a control processor operatively coupled to the transceivers and antenna(s), which is configured to select and utilize one or more of the wireless transceivers and associated communications protocols in order to transact particular transmissions, where the selection is based on characteristics of the particular transmissions, and to allocate bandwidth to multiple transmissions within a single communications protocol, where the allocation is based on characteristics of the transmissions. The device also includes a power source coupled to the transceivers and adapted to supply power to the transceivers.

Abstract: An integrated circuit (IC) device package is presented. A frame body has opposing first and second surfaces and a central opening that is open at the first and second surfaces. The second frame body surface is mounted to a first stiffener surface. An IC die is mounted to the first stiffener surface within the central opening through the frame body. A planar lid has opposing first and second surfaces. The second lid surface is coupled to the first frame body surface. A first substrate surface is coupled to a second stiffener surface. An array of electrically conductive terminals is coupled to a second substrate surface. The stiffener, frame body, and lid form an enclosure structure substantially enclosing the IC die. The die enclosure spreads heat from the IC die, and shields EMI emanating from and radiating toward the IC die. At least one tab protrudes from the second surface of the frame body. At least one receptacle formed in the first surface of the stiffener corresponding to the at least one tab.

Abstract: Apparatuses, methods, and systems for effective power management distribution are provided. In an embodiment, a system for providing power to a circuit block comprises a power management unit (PMU) configured on a first substrate and an integrated circuit (IC) configured on a second substrate. The PMU includes a first regulator configured to step down an input voltage and output a first regulated voltage. The IC includes the circuit block and a second regulator configured to receive the first regulated voltage and output a second regulated voltage. The second power regulated voltage provides power to the circuit block. The first regulator is more efficient than the second regulator.

Abstract: A system and method performs speed and connection handshaking between Beta signal ports and/or Bilingual ports in a serial data interface system. A tone pattern generator (e.g., a flip-flop) can be used to generate a tone pattern signal representing approximately 49 MHz to approximately 62 MHz. A selecting system (e.g., a multiplexer, a digital multiplexer, or the like) selectively transmits either the tone pattern signal or a data input signal. These signals include a driver control signal. A serializer serializes either the tone pattern signal or the data input signal. A clock device (e.g., a clock divider) drives the tone pattern generator and the serializer. A driver receives and differentially transmits, along a twister-wire pair, either the serialized tone pattern signal or the serialized data input signal.

Abstract: A method determines RW head radial position relative to tracks within a magnetic data disc. This involves sensing both a S-burst signal and a P-burst signal with the RW head. The S-burst signal and P-burst signal are associated with a two-burst servo pattern on the magnetic disc. The S-burst pattern has a phase that remains constant radially across tracks within the magnetic disc. The P-burst has a second phase that rotates radially across tracks within the magnetic disc. By determining a phase difference between a sensed S-burst signal and P-burst signal, it is possible to determine the RW head radial position relative to the tracks on the magnetic disc.

Abstract: Sub-matrix-based implementation of LDPC (Low Density Parity Check) decoder. A novel approach is presented by which an LDPC coded signal is decoded by processing 1 sub-matrix at a time. A low density parity check matrix corresponding to the LDPC code includes rows and columns of sub-matrices. For example, when performing bit node processing, 1 or more sub-matrices in a column are processed; when performing check node processing, 1 or more sub-matrices in a row are processed. If desired, when performing bit node processing, the sub-matrices in each column are successively processed together (e.g., all column 1 sub-matrices, all column 2 sub-matrices, etc.). Analogously, when performing check node processing, the sub-matrices in each row can be successively processed together (e.g., all row 1 sub-matrices, all row 2 sub-matrices in row 2, etc.).