Abstract: A method and apparatus are provided for enabling a transmitter to have a substantially linear magnitude response and a substantially linear phase response. The transmitter includes first and second power amplifier drivers (PADs) having respective first and second non-linear phase responses. The first non-linear phase response is based on a first bias applied to the first PAD, and the second non-linear phase response is based on a second bias applied to the second PAD. The first and second PADs are coupled in parallel to provide a combined substantially linear phase response. According to an embodiment, the first and second PADs have respective first and second average input capacitances. Signal swings about the first and second biases vary the respective first and second average input capacitances, which may be combined to provide a combined average input capacitance that is substantially insensitive to the signal swings about the first and second biases.

Abstract: Systems and methods that process and protect content are provided. In one example, a system may include, for example, a first device coupled to a second device. The first device may include, for example, an integrated circuit that may include a content processing system and a security system. The security system may include, for example, a digital rights manager. The first device and the second device may be part of a network. The network receives content and control information via the first device. The content processing system processes incoming content based upon at least the control information. The integrated circuit protects the content before placing the content on the network.

Abstract: A system (50) includes a communication path (170) and transmits data on a network (103, 106). A transmitter (101) transmits data on the network and a receiver (112) receives data from the network. A component (102, 114) in the communication path has a transfer characteristic (C1, C2, C3) adjusted in response to errors in data transmitted over and received from the network in order to reduce the error rate.

Abstract: A method of transmitting data packets over a non-dedicated local area network channel susceptible to random burst and/or white gaussian noise channel errors. Each data packet is encoded to form an error correctable encoded data packet, which is then interleaved, modulated and transmitted over the channel. The channel can be a telephone line. The encoding includes performing Reed Solomon encoding on each data packet to form Reed Solomon error correctable encoded data packets. Each data packet is cyclic redundancy check encoded prior to performing Reed Solomon encoding. Also disclosed is a corresponding method of receiving data packets over a non-dedicated local area network channel, and a corresponding system for transmitting and receiving data packets over a non-dedicated local area network channel.

Abstract: Disclosed herein is a redundant network and communication protocol at least including host computers, RF base stations, and roaming terminals. The network may utilize a polling communication protocol such that under heavy traffic conditions, a roaming terminal wishing to initiate communication may be required to determine whether the channel is clear by listening for an entire interpoll gap time. When a hidden terminal is communicating, the roaming terminal may conclude that the communication is taking place upon receiving a polling frame directed to the hidden terminal from the normally silent base station. Inherent redundancy techniques may be used with a spanning tree approach for determining the most efficient pathways from a source to a destination and ensuring that the network adapts to spatial changes or breakdowns within the network.

Abstract: Aspects of a method and system for digital to analog conversion for power amplifier driver amplitude modulation are presented. Various aspects of the system may include circuitry that enables oversampling, within a single integrated circuit device, of each of a plurality of samples in a digital baseband signal. The circuitry may enable reduction of a number of bits, i.e., coarse quantization, in each of the oversampled plurality of samples so as to cause displacement of the quantization noise that occurred as a result of the coarse quantization. A subsequent signal may be generated based on the oversampled signal. The circuitry may enable the subsequent signal to be low-pass filtered utilizing filter circuitry in the single integrated circuit device, thereby attenuating the quantization noise displaced into the higher frequency range of the oversampled signal.

Abstract: A circuit with dielectric thicknesses is presented that includes a low-pass filter including one or more semiconductor devices having a thick gate oxide layer, while further semiconductor devices of the circuit have thin gate oxide layers. The low-pass filter semiconductor device includes an N-type substrate, a P-type region formed on the N-type substrate, a thick gate oxide layer formed over the P-type region, a P+ gate electrode formed over the thick gate oxide layer and coupled to a first voltage supply line, and P+ pick-up terminals formed in the P-type region adjacent the gate electrode and coupled to a second voltage supply line. The low-pass filter semiconductor device acts as a capacitor, whereby a gate-to-substrate voltage is maintained at less than zero volts to maintain a stable control voltage for the circuit.

Abstract: A multi-speed burst mode serializer/de-serializer (SerDes). A configurable SerDes can be designed to operate in one of a plurality of operating modes. The plurality of operating modes correspond to the reception of signals from optical network units that operate at different nominal speeds.

Abstract: Systems and methods for embedded tamper mesh protection are provided. The embedded tamper mesh includes a series of protection bond wires surrounding bond wires carrying sensitive signals. The protection bond wires are positioned to be vertically higher than the signal bond wires. The protection wires may be bonded to outer contacts on the substrate while the signal bond wires are bonded to inner contacts, thereby creating a bond wire cage around the signal wires. Methods and systems for providing package level protection are also provided. An exemplary secure package includes a substrate having multiple contacts surrounding a die disposed on an upper surface of the substrate. A mesh die including a series of mesh die pads is coupled to the upper surface of the die. Bond wires are coupled from the mesh die pads to contacts on the substrate thereby creating a bond wire cage surrounding the die.

Abstract: A graphics integrated circuit chip is used in a set-top box for controlling a television display. The graphics chip processes analog video input, digital video input, graphics input and audio input simultaneously. The system includes a video decoder having a chroma-locked sample rate converter. The chroma-locked sample rate converter converts the samples to those taken at a sample rate that is a multiple of the chroma subcarrier frequency and that is locked to chroma bursts of the analog video signal in a control loop. The video decoder also includes a line-locked sample rate converter that receives samples at a multiple of the chroma subcarrier frequency and converts the samples to samples with a sample frequency that is a multiple of the horizontal line rate of the video input. The line-locked sample rate converter measures the horizontal line rate to an accuracy of a fraction of a pixel and adjusts the sample rate and phase of the line-locked sample rate converter to produce accurate line-locked samples.

Abstract: Presented herein are systems and methods for clock rate determination. A bitstream is sampled by sampling a transmitted clock signal at a rate corresponding to a receiver clock signal, and measuring an average number of consecutive samples that have a same state selected from a first state and a second state.

Abstract: Systems and methods for synchronizing a receive clock signal phase with a transmit clock signal phase are presented. A system includes a receiving channel and a transmitting channel, wherein the transmitting channel synchronizes a transmit clock signal phase with a receive clock signal phase based on receive clock signal phase data. A method includes storing a previous receive clock signal phase of a receiving channel and identifying a current receive clock signal phase of the receiving channel. The method further includes determining a phase difference between the previous receive clock signal phase and the current receive clock signal phase, and identifying a direction of the phase difference. The method further includes adjusting a previous transmit clock signal phase of the transmitting channel to a current transmit clock signal phase of the transmitting channel based on the phase difference and direction.

Abstract: A Bluetooth host solves the aforementioned problems by evaluating a Bluetooth service provider server ID and by determining which of a plurality of access IDs map to the server ID and, correspondingly, providing a Bluetooth access ID that corresponds thereto. Accordingly, one Bluetooth host may readily gain access to any one of a plurality of different devices and different types of devices. Additionally, the Bluetooth host includes capacity to store and provide additional supporting information according to the type of device that is the Bluetooth service provider. Generally, the Bluetooth host stores a plurality of access or link IDs in relation to a plurality of master device IDs and, upon detecting a beacon, determines what access or link ID to provide and whether to provide additional stored information.

Abstract: The invention relates to an interleaved track and hold circuit for tracking and holding a value of a continuous input signal and to provide discrete values thereof, wherein the circuit comprises a first and a second stage. To avoid tones caused by differences in the non-ideal elements when switching through several parallel second stages the circuit according to the invention comprises a single first stage and at least two second stages.

Abstract: A communications receiver architecture characterized by a relatively low intermediate frequency (IF) and a polyphase filter. The receiver includes an input amplifier coupled to a carrier signal. Respective I and Q demodulators are coupled to the output of the input amplifier. A quadrature local oscillator (LO) generator provides respective LO_I and LO_Q inputs to the I demodulator and LO_Q inputs to the I demodulator and to the Q demodulator. The quadrature LO generator is driven by a phase-locked LO, and the LO frequency is such that an IF of, in one embodiment, approximately 1 MHz results. The I demodulator and Q demodulator outputs are applied through respective AID converters to a polyphase filter. The polyphase filter outputs are then processed by a digital I/Q demodulator.

Abstract: An integrated circuit radio transceiver comprises an integrated phase shift mixer for generating a phase and frequency shifted output signal to at least a portion of one of a transmitter or receiver front end. The integrated phase shift mixer includes a phase shift block that is operable to produce a phase shifted current signal at an output of the phase shift block and a mixer that is operable to produce the phase and frequency shifted output signal based upon the phase shifted current signal. One aspect of the present invention is that the phase shift block produces an output as a current signal and the mixer block is operably disposed and formed to receive the current signal produced by the phase shift block. Thus, the mixer includes a folded cascode mixer that provides a substantially low input impedance.

Abstract: A method for multiplying, at an execution unit of a processor, two complex numbers in which all four scalar multiplications, concomitant to multiplying two complex numbers, can be performed in parallel. A real part of a first complex number is multiplied at the execution unit by a real part of a second complex number to produce a first part of a real part of a third complex number. An imaginary part of the first complex number is multiplied at the execution unit by an imaginary part of the second complex number to produce a second part of the real part of the third complex number. A first arithmetic function is performed at the execution unit between the first part of the real part of the third complex number and the second part of the real part of the third complex number. The imaginary part of the first complex number is multiplied at the execution unit by the real part of the second complex number to produce a first part of an imaginary part of the third complex number.

Abstract: Configuring a multiple stage band pass filter of a radio frequency receiver commences by setting a corner of a low pass mixer output filter that receives a down sampled analog information signal. Operation continues with setting a buffer output filter corner of a low pass buffer output filter coupled to an output of low pass mixer output filter via a buffer. Then, operation includes setting the poles and zero of a plurality of band pass filters coupled to the output of the low pass buffer output filter is performed. This operation includes first setting a zero of a respected band pass filter and then setting the plurality of poles of the band pass filter. Finally, operation concludes with setting a combined gain of the combination of the low pass mixer output filter, the low pass buffer output filter, and the plurality of band pass filters.

Abstract: Methods for removing complexity from a Bluetooth processor's firmware and placing them in hardware in order to use a simplier processor or to do other tasks in the Bluetooth processor. Assembling and managing communication packets and transmission, providing modulo divides, and allocating memory are typical firmware tasks for a Bluetooth device. By creating circuits that assemble and manage communications packets and transmits, provide modulo divides, and manage Bluetooth device memory a processing burden can be removed from the Bluetooth processor. This lessened processing requirement allows less expensive, e.g. slower, processors to be used, or other functions to be incorporated into the processor's firmware.

Abstract: An integrated circuit radio transceiver includes a phase shift block that is operable to produce a phase shifted current signal at an output of the phase shift block and a mixer with a low input impedance that is operable to produce a phase and frequency shifted output current signal based upon the phase shifted current signal. One aspect of the present invention is that the phase shift block produces an output as a current signal and the mixer block is operably disposed and formed to receive the current signal produced by the phase shift block. Similarly, an operational amplifier configured in a low input impedance mode is provided to receive and amplify a current signal mixer output, all to maximize signal processing head room reduce circuit noise and improve linearity.