Abstract: A method for multiplying, at an execution unit of a processor, two complex numbers in which a real part and an imaginary part of a product of the multiplying can be stored in a same register of the processor. First data is conveyed along at least a first interconnect of the processor. The first data has a first operand. The first operand represents a first complex number. Second data is conveyed along at least a second interconnect of the processor. The second data has a second operand. The second operand represents a second complex number. The first operand is multiplied at the execution unit by the second operand to produce a first result. The first result represents a third complex number. Third data is stored at a first register of the processor. The third data has the first result. The first result has at least the product of the multiplying.

Abstract: An apparatus and method is disclosed to calculate the actual received desired channel power from the downstream transmit power of a Cable Modem Termination System (CMTS) when operating at the nominal line voltage and/or at the normal room temperature as per the DOCSIS specification. A Set-top Device produces a Downstream Power Management (DPM) gain measurement signal having a known power level. The Set-top Device embeds the DPM gain measurement signal onto a received downstream multi-channel communication signal. After embedding the DPM gain measurement signal onto the downstream multi-channel communication signal, the Set-top Device downconverts the combined DPM gain measurement signal and downstream multi-channel communication signal to recover one or more communication channels containing information of a broadcast.

Abstract: Cross-coupled low noise amplifier for cellular applications. A circuitry implementation that includes two pairs of metal oxide semiconductor field-effect transistors (MOSFETs) (either N-type of P-type) operates as an LNA, which can be used within any of a wide variety of communication devices. In one embodiment, this design is particularly adaptable to cellular telephone applications. A majority of the elements are integrated within the design and need not be implemented off-chip, and this can provide for a reduction in area required by the circuitry. A very high output impedance is provided by using two transistors (implemented in a triple well configuration) with resistive source degeneration. A higher than typical power supply voltage can be employed (if desired) to accommodate the voltage drops of the resistors and transistors.

Abstract: A fractal antenna array based on a modified Peano-Gosper curve. The fractal antenna array is constructed using a 100-segment fractal curve that has the fractal expansion in a linear direction.

Abstract: High speed, low power all CMOS thermometer-to-binary demultiplexer. A received signal undergoes digital sampling (e.g., as within an ADC) to generate a signal that subsequently undergoes encoding (e.g., transformation from thermometer encoded data to binary encoded data) and de-multiplexing. Two separate de-multiplexing stages are employed when performing combined encoding and de-multiplexing. In addition, the individual DEMUXs of the two stages are clocked using a distributed clock generation architecture, such that, reset and time-interleaving is controlled on the ADC clock generator. The thermometer-to-binary encoders are placed very close to the input stage which facilitates very fast data rates while consuming relatively lower power.

Abstract: A wireless communication device processes N Radio Frequency (RF) bursts contained within N slots of a digital communications time divided frame, wherein N is a positive integer greater than one. The wireless communication device includes an RF front end, a baseband processor, and an equalizer module. The RF front end is operable to receive the plurality of received RF bursts and to convert the RF bursts to corresponding baseband signals. The baseband is operable to receive the baseband signals, to pre-equalization process the baseband signals to produce processed baseband signals, and to post-equalization process soft decisions. The equalizer module is operable to equalize the processed baseband signals to produce the soft decisions. These RF bursts may be contained in adjacent slots or, in non-adjacent slots, or in a combination of adjacent slots and non-adjacent slots.

Abstract: A decoder for decompressing real-time media data streams and a method for operating such a decoder is disclosed. The decoder may comprise a relatively larger first memory for storing compressed data and parameters, and a processor for executing a decompression algorithm, the processor having a relatively smaller second memory. The decompression algorithm may be executed on a periodic basis, and the parameters used to select the data to be decompressed may be moved from the second memory to the first memory each time the decompression algorithm executes. An embodiment of the present invention may use slower, less expensive memory to enable it to support a greater number of real-time media streams than prior art solutions. Another embodiment of the present invention may include machine-readable storage having stored thereon a computer program having a plurality of code sections executable by a machine for causing the machine to perform the foregoing.

Abstract: Maximum likelihood detection of signals in a MIMO receiver. A system transformation is obtained by selecting a weighting matrix that when linearly transforming a channel utilized for wireless communication, results in a particular transformed triangular matrix. The weighting matrix is then used to provide a transformed vector for a received signal that allows a search in one constellation. In searching the constellation recursion values are used to calculate the Euclidean distances between set points of the constellation and the location on the constellation corresponding to the received signal for both bit values 0 and 1. Minimum Euclidean distances are determined for bit values 0 and 1 and the difference of the minimum Euclidean distances is used to compute the maximum likelihood value for bits contained in the received signal.

Abstract: The wide bandwidth transceiver includes a receiver section, a transmitter section, and a local oscillation module. The local oscillation module generates a first and a second local oscillation. The transmitter section converts an outbound baseband signal and/or a low intermediate frequency (IF) signal into a first outbound radio frequency (RF) signal based on the second local oscillation when the wide bandwidth transceiver is in a second wireless standard mode and converts the outbound baseband and/or the low IF signal into a second outbound RF signal based on the first and second local oscillations when the wide bandwidth transceiver is in a first wireless standard mode.

Abstract: According to one exemplary embodiment, a three-way splitter includes a printed element and a resistive network comprising discrete resistors. A first printed branch, second printed branch, and third printed branch distribute a received communication signal to respective outputs having substantially the same phase, frequency, and impedance. Each printed branch includes a number of substantially ninety-degree angles. In one embodiment, the printed branches are quarter wavelength transmission lines in a frequency range of 1.5 GHz. In one embodiment, the three-way splitter consumes less than one square inch of surface area on a printed circuit board, and can be used in a satellite receiving system, for example. In this embodiment, the three-way splitter is utilized for frequencies in the range of approximately 900 MHz to 2.2 GHz.

Abstract: A physical layer device (PLD) includes a first serializer-deserializer (SERDES) device and a second SERDES device. Each SERDES device includes an analog portion with a serial port that is configured to communicate serial data with various network devices, and a digital portion that is configured to communicate parallel data with other various network devices. The PLD includes a first signal path that is configured to route serial data signals between the analog portions of the SERDES devices, bypassing the digital portions of the SERDES devices. Therefore, the SERDES devices can directly communicate serial data without performing parallel data conversion. A second signal path is configured to route recovered clock and data signals between the analog portions of the SERDES devices, but still bypassing the digital portions of the SERDES devices. The recovered clock and data signals are then regenerated before being transmitted over a network device.

Abstract: According to the present invention, the bandwidth of a TDD channel is increased where multiple slave devices communicate with a master device over the channel. According to an aspect of the present invention, the master device can increase channel bandwidth by utilizing available transmit slots that occur during receipt of a multi-slot packet from a slave device. For example, the master device receives a first packet at a first frequency from a first slave via the channel. The master determines whether the first packet is a multi-slot packet, and if so, transmits a second packet to a second slave via the channel at a second frequency different from the first frequency. The second packet is transmitted after receipt of the first packet, but prior to the end of the first packet.

Abstract: An exemplary embodiment of the present invention described and shown in the specification and drawings is a transceiver with a receiver, a transmitter, a local oscillator (LO) generator, a controller, and a self-testing unit. All of these components can be packaged for integration into a single IC including components such as filters and inductors. The controller for adaptive programming and calibration of the receiver, transmitter and LO generator. The self-testing unit generates is used to determine the gain, frequency characteristics, selectivity, noise floor, and distortion behavior of the receiver, transmitter and LO generator. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or the meaning of the claims.

Abstract: An integrated circuit includes a millimeter wave transceiver section that is coupled to generate a first modulated RF signal from a first outbound symbol stream and to convert a first inbound RF signal into a first inbound symbol stream. A wireless transceiver section is coupled to generate a second modulated RF signal from a second outbound symbol stream and to convert a second inbound RF signal into a second inbound symbol stream. A processing module is coupled to convert first outbound data into the first outbound symbol stream, convert second outbound data into the second outbound symbol stream, convert the first inbound symbol stream into first inbound data, and to convert the second inbound symbol stream into second inbound data.

Abstract: Systems and methods that provide satellite-based media processing are described. In one embodiment, a system that exchanges media may include, for example, a communications device that may be coupled to a network and to an antenna. The communications device may provide two-way communications with the network and may provide one-way communications with the antenna. The communications may receive media content from the antenna and/or the network.

Abstract: A method for transmitting data in an xDSL system is disclosed. In an exemplary embodiment, the method includes defining a data transmission unit (DTU) to be sent in an xDSL data stream, defining a retransmit container as a time slot that corresponds to a sent DTU, maintaining a copy of the sent DTUs and an index of corresponding retransmit containers in retransmission buffer, transmitting the DTUs in the xDSL data stream, determining whether a transmitted DTU should be retransmitted, identifying each corrupted DTU by its corresponding retransmit container, and retransmitting an uncorrupted copy of the DTU as identified by the corresponding retransmit container. The retransmission is deferred until the DTU is at a predefined position in the retransmission buffer.

Abstract: A dual purpose serializer/de-serializer (SerDes) for point-to-point and point-to-multipoint communication. A configurable SerDes can be designed to operate in one of a plurality of operating modes. Selection between the plurality of operating modes can be based on information received via a management interface. In one example, the various operating modes can be defined with different locking times and jitter characteristics.

Abstract: A graphics integrated circuit chip is used in a set-top box for controlling a television display. The graphics chip processes analog video input, digital video input, graphics input and audio input simultaneously. A video scaling system preferably conserves memory by downscaling video prior to capturing the video in memory and upscaling video after the video is called out of memory.

Abstract: An off-load engine for processing a packet conveyed between a target and a network over a transport connection, the packet including a payload and a header. The engine includes a payload buffer, for holding data exchanged between the off-load engine, the network, and the target for inclusion in the payload, and a packet processor, for processing context of the transport connection. The engine also includes a context buffer, for holding the context processed by the packet processor, a memory access multiplexer, which is coupled to convey the data in the payload buffer and the context in the context buffer to and from a memory that stores both the data and the context, and an arbiter, which controls the multiplexer by arbitrating among payload requests to convey the data between the payload buffer and the memory and context requests to convey the context between the context buffer and the memory.

Abstract: Aspects of a method and system for enhancement of power amplifier (PA) efficiency through controlled variation of gain in a power amplifier driver are presented. Aspects of the system may comprise an envelope detector that enables detection of an amplitude of an analog input signal. The envelope detector may enable computation of a first gain value based on the detection. A second gain value may be computed based on the first gain value. A PA may enable generation of an analog output signal based on the analog input signal, the first gain value and the second gain value.