Abstract: A wireless transceiver includes a plurality of antennas. A plurality of signal recovery circuits generate a selected number of received signals from a first subset of the plurality of antennas, based on a control signal. A receiver section recovers an inbound data stream from the selected number of received signals. A plurality of transmitter sections generate a selected number of transmitted signals to a second subset of the plurality of antennas, based on the control signal, wherein the intersection between the first subset of the plurality of antennas and the second subset of the plurality of antennas is the null set for each value of the control signal.

Abstract: An integrated circuit includes an integrated circuit die having a millimeter wave transceiver for communicating with a remote device via millimeter wave RF signaling. An antenna section facilitates the RF signaling, wherein the antenna section includes at least one bonding wire. A substrate is coupled to support the first integrated circuit die.

Abstract: A mobile communication device includes a processing module that executes a gaming application based on gaming data and that generates display data in response thereto. At least one transceiver sends the display data to a display device in a gaming mode of operation and transceives wireless telephony data with a wireless telephony network in a telephony mode of operation.

Abstract: A transceiver includes a far field transceiver section, when engaged, transceives first data with a remote device via far field signaling. A near field transceiver section, when engaged, transceives second data with the remote device via near field signaling. A communication control module selectively engages the far field transceiver section and the near-field transceiver section.

Abstract: An integrated circuit includes a plurality of circuits including a plurality of millimeter wave interfaces for communicating data between the plurality of circuits via millimeter wave RF signaling. A power supply line supplies at least one power supply signal to the plurality of circuits. The power supply line includes a plurality of antenna elements to facilitate the communicating of first data between the plurality of circuits via the millimeter wave RF signaling.

Abstract: A side channel attack utilizes information gained from the physical implementation of a cryptosystem. Software and hardware-based systems and methods for preventing side channel attacks are presented. Cryptographic hardware may introduce dummy operations to compensate for conditional math operations in certain functions such as modular exponentiation. Cryptographic hardware may also introduce random stalls of the data path to introduce alterations in the power profile for the operation. A cryptographic function may be mapped to a micro code sequence having a plurality of instructions. Firmware in the cryptosystem may alter the micro code sequence by altering the order of instructions, add dummy operations in the micro code sequence, break the micro code sequence into multiple sub micro code sequences and/or change the register location for source and destination operands used in the sequence. These alterations are designed to randomly change the timing and power profile of the requested function.

Abstract: Multi-band single-carrier modulation. A novel approach is presented by which interference compensation may be performed for signals received by a piconet operable device. The piconet operable device may be implemented within a region that includes two or more SOPs (Simultaneously Operating Piconets). Estimation of the level and location of interference is performed and the input to a decoder (within the piconet operable device) is selectively weighted to ensure that the effect of any existent interference within the signal received by the piconet operable device is minimized. Different interference levels are dealt with differently. For one example, portions of the received signal having undergone a large amount of interference may be simply treated as erasures with respect to the input the decoder. For another example, portions of the received signal having undergone some smaller degree of interference, but some interference nonetheless, may be de-weighted before being provided to the decoder.

Abstract: An integrated circuit includes a first integrated circuit die having a first circuit and a first intra-chip interface and a second integrated circuit die having a second circuit and a second intra-chip interface and a remote interface, wherein the first intra-chip interface and the second intra-chip interface electro-magnetically communicate first signals between the first circuit and the second circuit, and wherein the remote interface is coupled to engage in electromagnetic communications with a remote device. In an embodiment of the present invention, a shielding element shields the electromagnetic communications with the remote device from the electromagnetic communication of the first signals. In other embodiments, antenna beam patterns or differing polarizations are used to isolate the electromagnetic communications with the remote device from the electromagnetic communication of the first signals.

Abstract: Multi-code LDPC (Low Density Parity Check) decoder. Multiple LDPC coded signals can be decoded using hardware provisioned for a minimum requirement needed to decode each of the multiple LDPC coded signals. In embodiments where each LDPC matrix (e.g., employed to decode each LDPC coded signal) includes a common number of non-null sub-matrices, then a same number of memories are employed when decoding each LDPC coded signal. However, those particular memories employed can be different subsets for when decoding each LDPC coded signal. In embodiments where each LDPC code includes a different number of non-null sub-matrices within its respective LDPC matrix, then a different number of memories are employed when decoding each LDPC coded signal. Various degrees of parallelism in decoding can also be employed in which different numbers of bit engines and check engines can be employed when decoding different LDPC coded signals.

Abstract: A phase locked loop (PLL) a phase detector, a charge pump, a loop filter, a controlled oscillator, and a feedback divider. The phase detector is coupled to produce a difference signal based on a difference between phase of a reference oscillation and phase of a feedback oscillation. The charge pump is coupled to convert the difference signal into an up-signal or a down signal. The loop filter coupled to filter the up signal or the down signal to produce a control signal. The controlled oscillator is coupled to generate an output oscillation based on the control signal. The feedback divider is coupled to generate the feedback oscillation from the output oscillation based on a divider value. The loop filter includes a first resistor-capacitor circuit and a second resistor-capacitor circuit. The first resistor-capacitor circuit is calibrated using a first calibration technique and the second resistor-capacitor circuit is calibrated using a second calibration technique.

Abstract: An integrated data storage control system provides, in a single integrated circuit, RDC, servo logic, ATA interface, microprocessor, and other formerly discrete components in one highly integrated system design. The integrated circuit is rendered using a single integrated circuit technology type (e.g., digital CMOS) for all components. Analog and digital circuits are combined in such a way as to eliminate or reduce noise or interference in digital circuits from analog circuit components. Individual elements may have their outputs and inputs MUXed together such that individual elements can be selectively switched (during testing modes) such that the integrated circuit emulates or behaves in the same or similar manner as one of the prior art components. The present invention may be applied to magnetic hard disk drives (HDDs) or other types of storage devices such as floppy disk controllers, optical disk drives (e.g., CD-ROMs and the like), tape drives, and other data storage devices.

Abstract: A transmitter includes a dual mode modulator and an amplifier coupled to the dual mode modulator. The dual mode modulator implements a linear modulation scheme during a first mode of the modulator to produce a variable envelope modulated signal. The dual mode modulator implements a non-linear modulation scheme during a second mode of the modulator to produce a constant envelope modulated signal. The amplifier is biased as a linear amplifier during the first mode of the modulator and is biased as a non-linear amplifier during the second mode of the modulator. A feed-forward connection between the dual mode modulator and the amplifier is used to indicate a change in modulation mode and to adjust the bias of the amplifier. A power of the constant envelope modulated signal is increased such that an operating point of the amplifier remains substantially constant during the first and second modes of the modulator.

Abstract: A multiprocessor switching device substantially implemented on a single CMOS integrated circuit is described in connection with a channelized timer for use in controlling the issuance of signals to the processor(s) or control logic (such as interrupts, descriptors, etc.) that that identify system-related functions for a plurality of channels. Using control registers to select an individual bit of a multi-bit counter, a timing interval pulse is provided for prompting signal generation that is otherwise subject to a minimum count requirement.

Abstract: An FSK modulator and applications thereof are disclosed. The FSK modulator comprises a phase-locked loop, a frequency divider module, an image rejection mixer and a summing module. The phase-locked loop is operably coupled to generate a first oscillation from a reference oscillation. The frequency divider module is operably coupled to divide the first oscillation to produce a second oscillation. The image-rejection mixer is operably coupled to mix the second oscillation with a low intermediate oscillation to produce a mixed data signal, and the summing module is operably coupled to sum the mixed data signal with the first oscillation to produce an FSK modulated signal.

Abstract: A read/write timing generator includes a read/write signal generator for generating a read/write signal in response to the media event trigger of a disk drive and synchronized to a read/write bit clock. A read/write symbol clock generator adjusts a read/write symbol clock based on the read/write signal and the read/write bit clock.

Abstract: Systems and methods that prevent unauthorized access in a communications network are provided. In one embodiment, a system that prevents unauthorized access to a network device may include, for example, a network device and a headend. The headend may be coupled to a communications network. The network device may be deployed in a home environment and may be communicatively coupled to the communications network via the headend. The headend may be adapted, for example, to determine whether a request to access the network device is authorized.

Abstract: Improved decision feedback equalizer and decision directed timing recovery systems and methods suitable for use in connection with a dual mode QAM/VSB receiver system are disclosed. A trellis decoder operates in conjunction with a decision feedback equalizer circuit on trellis coded 8-VSB modulated signals. The trellis decoder includes a 4-state traceback memory circuit outputting a maximum likelihood decision as well as a number of intermediate decisions based upon the maximum likelihood sequence path. Any number of decisions, along the sequence, may be provided as an input signal to timing recovery system loops, with the particular decision along the sequence chosen on the basis of its delay through the trellis decoder. Variable delay circuitry is coupled to the other input of the timing recovery system loops in order to ensure that both input signals bear the same timestamp.

Abstract: A system includes a first bus segment and a second bus segment. The first bus segment is operatively coupled to one or more first bus agents, where the first bus agents are configured for writing messages to the first bus segment and reading messages from the first bus segment and the second bus segment, which is separate from the first bus segment, is operatively coupled to one or more second bus agents. The first bus agents are configured for writing messages to the first bus segment and reading messages from the first bus segment. The system also includes first electrical circuitry operably coupled to the first bus segment and the second bus segment and configured to read messages written on the first bus segment and to write the messages onto the second bus segment and second electrical circuitry operably coupled to the first bus segment and the second bus segment and configured to read messages written on the second bus segment and to write the messages onto the first bus segment.

Abstract: A system and method demodulate N QAM signals (N being a positive integer equal to or greater than 1) substantially simultaneously using, for example, one or two oscillators, regardless of how many QAM signals need to be demodulated.

Abstract: A differential preamplifier includes an active load with adjustable common-mode output level. The active load includes a transistor pair, a resistor pair, and a current source. The transistor load is employed to provide high gain, low offset, and a large bandwidth for the differential preamplifier. The resistor pair and current source are used to increase the common-mode output level of the differential preamplifier and to bias the transistor load. The current source can be varied to provide an adjustable common-mode output level suitable for driving next stage devices. The active load design allows the differential preamplifier to operate using only low power voltage supplies and with small-sized transistors.