Abstract: A bias filtering module with at least two capacitive levels satisfies both a settle time requirement and a filtering requirement using a voltage dependent filter module whose capacitance is a function of a voltage potential on the filtering circuitry output terminal. The final capacitance level is approximately three times larger than the initial capacitance level. MOS capacitors having a voltage dependent charge capacity within the bias filtering module are coupled between a plurality of bias lines and circuit common. In an alternate embodiment, a selectable first group of capacitors are switched into connection within the bias filtering module as a second group of capacitors approximately reach a fully charged state within a specified settle time to provide improved filtering.

Abstract: Presented herein are systems and methods for computing the product of a constant and a mixed number power of two. A circuit comprises a first register, a second register, a memory, a third register, and a multiplier circuit. The first register stores the constant. The second register stores the integer portion and the fraction portion. The memory stores a plurality of values, each of said plurality of values corresponding to a particular one of a corresponding plurality of fractions, wherein each one of said plurality of values is two to the exponential fraction corresponding to the one of said plurality of values. The third register stores a particular one of the plurality of values, said particular one of the plurality of values corresponding to the fraction portion. The multiplier circuit multiplies the contents of the third register by the contents of the first register, thereby resulting in a product.

Abstract: Aspects of the present invention allow the implementation of one or more data pools using portions or sectors of one or more hard disk drives. Aspects of the invention incorporate at least a method and system of implementing the one or more data pools. The method of implementing a data pool using one or more data storage drives may comprise first generating a first partition table and a second partition table, wherein the first partition table is a mirror image of said second partition table. The method further comprises second generating a first pool information block and a second pool information block, wherein the first pool information block is a mirror image of said second pool information block. The system of implementing a data pool using one or more data storage drives may comprise a memory, a software resident in the memory, and a processor capable of executing the software.

Abstract: A radio transmitter within a transceiver includes a digital processor and analog circuitry for modulating and transmitting an outgoing digital signal in multiple modes of operation. The digital processor digitally modulates the outgoing digital signal to produce one of a constant envelope modulated digital signal and a variable envelope modulated digital signal based on the particular modulation scheme being used to modulate the outgoing digital signal. In addition, the digital processor filters the outgoing digital signal using filter values selected based on the signal bandwidth of the outgoing digital signal. The analog circuitry converts digital envelope and phase signals of the modulated digital signal to analog envelope and phase signals, and up-converts the analog phase signal from an IF signal to an RF signal, using a loop filter that is programmable based on the signal bandwidth of the outgoing digital signal.

Abstract: A MIMO transceiver integrated circuit (IC) includes a plurality of multiple band direct conversion transmitter sections, a plurality of multiple band direct conversion receiver sections, and a local oscillation generation module. Each of the plurality of multiple band direct conversion transmitter sections includes a transmit baseband module and a multiple frequency band transmission module. Each of the plurality of multiple band direct conversion receiver sections includes a multiple frequency band reception module and a receiver baseband module. The local oscillation generation module is operably coupled to generate the first frequency band local oscillation when the multiple band MIMO transceiver IC is in a first mode and operably coupled to generate the second frequency band local oscillation when the multiple band MIMO transceiver IC is in a second mode.

Abstract: A radio receiver includes a low noise amplifier, a down conversion module, an analog to digital converter, and a digital demodulator. The digital demodulator is operably coupled to convert the digital low IF signals into inbound digital symbols and includes a baseband conversion module, a filtering module, a programmable equalizer, a CORDIC module, and a demodulation module. The programmable equalizer is operably coupled to equalize phase and frequency response of filtered digital baseband signals from the filtering module such that the phase and frequency response of the filtered digital baseband signals approximates phase and frequency response of a square root raised cosine filter to produce adjusted digital baseband signals. The CORDIC module is operably coupled to produce phase and magnitude information from the adjusted digital baseband signals. The demodulation module is operably coupled to produce the inbound digital symbols from the phase and magnitude information.

Abstract: Provided are a method and system for controlling impedance in a transconductance amplifier. A system includes a first transconductance amplifier and a second transconductance amplifier configured to control electrical characteristics associated with the first transconductance amplifier. An operational amplifier is provided and has at least one input port connected to the second transconductance amplifier. Also included is a first digital to analog converter (DAC) connected to receive a current signal from the operational amplifier.

Abstract: Methods and systems for 2D comb filtering of a PAL video signal are provided. The method may comprise generating a plurality of interpolated pixels for corresponding video samples in non-adjacent pixel lines for a video frame. At least one direction of least bandwidth may be determined among the video samples and the interpolated pixels. The method may blend combing in the determined direction of least bandwidth. A plurality of interpolated pixels for corresponding video samples may be generated in a first pixel line of the video frame. The plurality of interpolated pixels in the first pixel line may be shifted, so that each of the plurality of interpolated pixels in the first pixel line is one quarter cycle phase-shifted from a corresponding adjacent pixel in the first pixel line.

Abstract: The present invention is directed to a method for debugging scan testing failures of integrated circuits. The method includes identifying a bad scan path among a set of scan paths and segmenting the bad scan path into two segments. Once the bad scan path is segmented into two segments, scan tests are run to determine whether the source of errors is near the segment point. If the number of errors generated is below a threshold, the specific location of errors can be identified by tracing the errors either manually or automatically through an automated testing unit. If the source of errors is not near the segment point, the segment point is shifted based on an analysis of the errors on the good and bad scan paths. Additional scan tests are then run and the method repeated until the location of the source of errors is found.

Abstract: Certain embodiments of the invention may be found in a method for memory management for a mobile multimedia processor. The method may comprise receiving within a mobile multimedia processor chip a plurality of memory requests. The plurality of memory requests may be handled by allocating memory from at least one on-chip memory block and/or at least one off-chip memory block. The memory may be allocated based on a priority level of each of the plurality of memory requests and at least one dynamically settable global memory allocation priority threshold. A new dynamically settable global memory allocation priority threshold may be dynamically determined based on a new application and/or by monitoring at least one software process in at least one present application. Additionally, new memory request priority level may be dynamically determined for each memory request in at least one software process in a new application.

Abstract: A method and system to determine when a wireless terminal has been paged by a servicing base station. An encoded paging burst is received on a paging channel and then decoded to produce a decoded paging burst. The decoded paging burst is processed to determine if it is a null page. When the encoded paging burst is a null page, it is processed to produce a null page pattern. The wireless terminal may then enter a sleep mode or reduced functionality mode for a predetermined period of time. The wireless terminal awakes from the sleep mode to receive additional encoded paging bursts. Processing the additional encoded paging bursts produces a processed encoded paging burst, which is compared to the null page pattern. When compared favorably, the encoded paging burst is considered a null page, allowing the wireless terminal to re-enter the sleep mode without fully decoding the paging burst.

Abstract: An apparatus includes a plurality of memories, a plurality of systems, and a switch interface circuit. Each of the plurality of systems includes a memory controller coupled to a respective one of the plurality of memories. Additionally, each of the plurality of systems is coupled to at least one other one of the plurality of systems. Each of the plurality of systems further includes one or more coherent agents configured to access the plurality of memories, and wherein the plurality of systems enforce coherency across the plurality of systems for at least some accesses. At least one of the plurality of systems is coupled to the switch interface circuit separate from the interconnection of the plurality of systems. The switch interface circuit is configured to interface the apparatus to a switch fabric.

Abstract: Common circuitry supporting both bit node and check node processing in LDPC (Low Density Parity Check) decoder. A novel approach is presented by which a decoder may use the same circuitry to perform updating of edge messages with respect to bit nodes as well as updating of edge messages with respect to check nodes in the context of decoding LDPC coded signals. In addition, several very efficient architectures are presented to performing check node processing that involves the updating of edge messages with respect to check nodes. One embodiment performs check node processing using min** (min-double-star) processing in conjunction with min**? (min-double-star-minus) processing. Another embodiment performs check node processing using min†† (min-double-dagger) processing in conjunction with min†? (min-dagger-minus) processing. In addition, a single FIFO may be implemented to service a number of macro blocks in a parallel decoding implementation.

Abstract: Methods, systems, and apparatuses for calibration of analog to digital converters (ADC) are described herein. In an aspect, an ADC includes a plurality of slices. Each slice includes a digital to analog converter (DAC), a comparator, and a digital processing unit (DPU). The digital processing unit is electrically connected to the comparator and the DAC. In another aspect, an analog-to-digital converter includes an input module and an analog to digital converter core configured to receive an analog input from the input module and generate a digital output. The ADC is configured to adjust a precision of the analog to digital converter core based on a quality of the analog input signal.

Abstract: Switching between communication ports of a notebook is typically accomplished using an off-chip local area network (LAN) switch or an off-chip high speed analog multiplexer. This off-chip component is disadvantageous for several reasons, including: added cost of an additional component; increased overall power consumption because transmit amplitude loss; and reduced cable reach and link performance due to hybrid mismatch and signal distortions. To reduce cost and preserve electrical and networking performance, an integrated switch is provided to multiplex signals of a networking communication chip to multiple network paths.

Abstract: In a wireless communication system, the time required to establish network connectivity for subscriber stations can be reduced by prioritizing and/or reducing contention between the subscriber stations. The subscriber stations can be divided into acquisition groups and assigned specific uplink channels on which to range. The subscriber stations can randomly or pseudo-randomly range on uplink channels.

Abstract: A single chip wireless transceiver operable to perform voice, data and radio frequency (RF) processing is provided. This processing may be divided between various processing modules. This single chip includes a processing module having an ARM microprocessor and a digital signal processor (DSP), an RF section, and an interface module. The processing module converts an outbound voice signal into an outbound voice symbol stream, converts an inbound voice symbol stream into an inbound voice signal, converts outbound data into an outbound data symbol stream, and converts an inbound data symbol stream into inbound data. These functions may be divided between the ARM microprocessor and DSP, where the DSP supports physically layer type applications and the ARM microprocessor supports higher layer applications. Further bifurcation may be based on voice applications, data applications, and/or RF control.

Abstract: A system and method for accelerated handling of masked store operations in a processor or processor-based system/chip are described. A set of instructions that support a store operation under a per-byte predicate mask is provided. The invention accelerates the handling of small transfers at arbitrary alignments, such as those used by xDSL modems to deal with ATM cells or Reed Solomon codewords.

Abstract: A voice data and RF integrated circuit (IC) includes a memory module that stores a least one application as a plurality of operational instructions, the at least one application having a plurality of power modes that each correspond to one of a plurality of use characteristics. A processing module executes the plurality of operational instructions and that determines a selected one of the plurality of power modes based on current use characteristics of the at least one application, and generates a power mode signal based on the selected one of the plurality of power modes. An on-chip power management circuit receives the power mode signal and that generates a plurality of power supply signals based on the power mode signal.

Abstract: An audio codec integrated with baseband processing and RF on a single IC chip. The audio codec may be implemented in a variety of wireless transceivers, such as cell phones, to offer voice, data and/or music functions. The codec also has monaural and stereo channels for audio output, as well as stereo inputs.