Abstract: A radio frequency (RF) front-end includes a power amplifier module and a power amplifier control module. The power amplifier module is coupled to amplify an outbound RF signal in accordance with a control signal to produce an amplified outbound RF signal. The power amplifier control module is coupled to generate the control signal based on at least one of forward power of the amplified outbound RF signal and reflected power of the amplified outbound RF signal.

Abstract: A radio frequency integrated circuit (RFIC) includes a silicon substrate, CMOS processing circuitry, and a bipolar power amplifier module. The CMOS processing circuitry is on the silicon substrate. The bipolar power amplifier module is on the silicon substrate and is operable in a 5 GHz frequency band.

Abstract: An integrated circuit radio transceiver and method therefor includes capacitive loop filter with selectable capacitive elements that are operable to adjust a signal level provided to a voltage controlled oscillator to control a frequency of an output signal of the oscillator. A plurality of switches are controlled by logic to define a discharge mode, a charge mode and charge sharing mode in which a plurality of capacitive elements share charge while generating the input voltage to the oscillator.

Abstract: A receiver includes a plurality of RF receiver modules, a plurality of analog baseband sections, a plurality of analog to digital conversion sections, and a digital baseband processing module. The RF receiver modules convert inbound RF signals into a plurality of inbound analog signals. When the receiver is in a first mode, one of the plurality of analog baseband sections is active to adjust one of the plurality of inbound analog signals to produce an adjusted inbound analog signal; one of the plurality of analog to digital conversion sections converts the adjusted inbound analog signal into an inbound digital signal; and a portion of the digital baseband processing module is active to convert the inbound digital signal into inbound data.

Abstract: Intended for an information security application, particularly in networked information systems, the present invention includes two methods and systems for verifying a current performance of a command by a controller. A first cyclic redundancy check (CRC) for the command is prestored in memory. A second CRC for the command is calculated after instructions of the command have been performed by the controller. The first CRC is compared with the second CRC. Preferably, the controller is reset if the first CRC does not match the second CRC. Also, an address of a first instruction of the command is compared with an address of a second instruction of the command to determine if there may be a discontinuity between the first and the second instructions. It is determined if the first instruction is a valid instruction from/to which an instruction sequence of the command can be redirected.

Abstract: A radio frequency (RF) front-end includes a plurality of power amplifier modules and a plurality of impedance matching circuits. Each of the plurality of impedance matching circuits includes an input connection and an output connection, wherein outputs of the plurality of power amplifier modules are coupled to corresponding input connections of the plurality of impedance matching circuits to provide a desired loading of the plurality of power amplifier modules and wherein the output connections of the plurality of impedance matching circuits are coupled together to add power of the plurality of power amplifiers.

Abstract: Disclosed herein is a redundant network and communication protocol at least including host computers, RF base stations, and roaming terminals. The network may utilize a polling communication protocol such that under heavy traffic conditions, a roaming terminal wishing to initiate communication may be required to determine whether the channel is clear by listening for an entire interpoll gap time. When a hidden terminal is communicating, the roaming terminal may conclude that the communication is taking place upon receiving a polling frame directed to the hidden terminal from the normally silent base station. Inherent redundancy techniques may be used with a spanning tree approach for determining the most efficient pathways from a source to a destination and ensuring that the network adapts to spatial changes or breakdowns within the network.

Abstract: Systems and methods that provide self-describing transport protocol segments are provided. In one embodiment, a system that handles transport protocol segments may include, for example, a sender that adapts a transport protocol segment. The transport protocol segment may include, for example, a self-describing header and an indicator. The indicator may indicate at least one of the presence and the location of the self-describing header.

Abstract: Aspects of the pattern-independent phase adjustment system includes a single output data XOR gate coupled to a differential input data signal and a bias voltage through a first variable resistor. A single output reference XOR gate may be coupled to a latched differential input signal and the bias voltage through a second variable resistor. At least one latch may be coupled to at least one differential input of the data and reference XOR gate. The single output of the data XOR gate may be a data output of a clock and data recovery circuit (CDR) and the single output of the reference XOR gate may be a reference output of the clock and CDR. No current may flow at the data output of the data XOR gate and the reference output of the reference XOR gate when there are no transitions occurring at an input of the phase detector.

Abstract: A method for regulating a voltage in an integrated circuit device includes providing a first regulated output based upon a first voltage input range and subsequently receiving the first regulated output and providing a second regulated output based upon a second voltage input range of the first regulated output. A circuit is further provided that operates accordingly. Additionally, a clipper circuit is provided at the input to protect for over voltage conditions that may results, for example, from a charging battery to cause an output voltage of the battery to substantially exceed ordinary output voltage levels.

Abstract: A closed-loop circuitry includes, in part, a loop filter and a current source/sink coupled to the loop filter to adjust the phase/frequency of the signal generated by the closed-loop circuitry. Because the voltage generated by the loop filter has a relatively low frequency, the current source/sink is operable at a relatively low frequency. Each current source and current sink may be a current digital-to-analog (DAC). The amount of current sourced into or sunk out of the loop filter by the current DAC is varied by setting the associated bits of a multi-bit signal. If the closed-loop circuitry is differential, a current source is coupled to the loop filter adapted to receive the differentially high signal, and a current source is coupled to the loop filter adapted to receive the differentially low signal.

Abstract: Presented herein is a system for storing macroblocks for such that all vertically, horizontally, and diagonally adjacent macroblock are stored in different banks. When fetching a block from a reference frame that overlaps four macroblocks, each of the overlapped macroblocks can be fetched substantially concurrently.

Abstract: A balun that includes a first conductor, a second conductor and a third conductor. The first conductor has a first length. The first conductor also has a first end connected to a first balanced power amplifier output port. The second conductor has substantially the same first length. The second conductor also includes a first end connected to a second balanced power amplifier output port and a second end connected a second end of the first conductor. The third conductor has substantially the same first length. The third conductor has a first end connected to an antenna port and a second end connected to a ground potential.

Abstract: An integrated circuit radio transceiver and method therefor includes a high-pass variable gain amplifier (HPVGA) operably disposed within one of the transmitter and the receiver front ends operable to provide a linear variable gain and a substantially constant high-pass frequency corner that does not vary with changes in gain level settings. The HPVGA includes an amplifier operably disposed to receive an input signal and to produce an amplified output based upon the input signal, an adjustable resistance block operable to adjust resistance based upon a gain control input and corner drift compensation block operably disposed to provide corner frequency compensation at the input terminal of the amplifier that is further coupled to receive the input signal from the adjustable resistance block.

Abstract: Digital signal processing generates IF modulated digital data which is then converted to analog using a high sample rate digital-to-analog converter (DAC) without first producing a baseband signal that is to be upconverted to IF. The digital data has a high sample rate that is a whole multiple of a specified IF signal. A DAC converts the digital data into a continuous waveform IF signal that is produced to a feed-forward filter that eliminates spectral copies of the signal. The sample rate is selected so that harmonic signals do not appear in specified signal bands. Various embodiments include sample rates of 104 and 338 MHz (GSM application). The 26 MHz IF filtered signal produced by the feed-forward filter is then produced to a translational loop that produces a corresponding output oscillation (RF transmit signal).

Abstract: A startup protocol is provided for use in a communications system having a plurality of transceivers, one transceiver acting as a master and another transceiver acting as slave, each transceiver having a noise reduction system, a timing recovery system and at least one equalizer. The operation of the startup protocol is partitioned into three stages. During the first stage the timing recovery system and the equalizer of the slave are trained and the noise reduction system of the master is trained. During the second stage the timing recovery system of the master is trained in both frequency and phase, the equalizer of the master is trained and the noise reduction system of the slave is trained. During the third stage the noise reduction system of the master is retrained, the timing recovery system of the master is retrained in phase and the timing recovery system of the slave is retrained in both frequency and phase.

Abstract: A Decision Feedback Equalizer (DFE) system includes a DFE and a DFE coefficients processor. The DFE receives an uncompensated signal and operates upon the uncompensated input using DFE coefficients to produce an equalized output. The DFE coefficients processor formulates a channel estimate as a convolution matrix H. The DFE coefficients processor determines a Feed Back Equalizer (FBE) energy constraint based upon the channel estimate. The DFE coefficients processor relates the convolution matrix H to the DFE coefficients in a matrix format equation, the matrix format equation based upon the structure of the DFE, the convolution matrix, an expected output of the DFE, and the FBE energy constraint. The DFE coefficients processor formulates a recursive least squares solution to the matrix format equation and computes the recursive least squares solution to the matrix format equation to yield the DFE coefficients.

Abstract: A dual-band input transceiver block is formed to operably receive one of a 2.4 GHz radio frequency signal or a 5.0 GHz radio frequency transceiver signal in a manner that minimizes duplication of circuitry and creates a combined circuit path for RF front end input stages for much of the input stage. The embodiments include separate amplification and mixing stages whose outputs are combined by a stabilized load with circuitry for removing a common mode feedback signal. A first input section is operably coupled to receive a first local oscillation input and a first frequency band signal input. A second input section is coupled to receive a second local oscillation input and a second frequency band signal input. Outputs of the first and second input sections are produced to a stabilized load with a common mode feedback block for removing a common mode feedback signal.

Abstract: A method and apparatus for an automatic gain control circuit (AGC) that utilizes freezing and unfreezing states. A freezing process moves the AGC into a TRANSITION state from a NORMAL state, based on net change of VGA gain control codes over a monitoring time window. The freezing process then moves the AGC into a FROZEN state from the TRANSITION state, based on net change of VGA gain control codes over the monitoring time window. An unfreezing process moves the AGC into the NORMAL state from the FROZEN state, based on signal amplitude changes at the output of the VGA or other parameters of the VGA.

Abstract: A system and method for de-interleaving data in a wireless receiver, wherein a single memory buffer is coupled to a read/write unit that performs both first and second de-interleaving operations. According to a first aspect of the present invention, the read/write unit performs the second de-interleaving operation as data is written to the memory buffer, and performs the first de-interleaving operation as data is read from the memory buffer. According to a second aspect of the present invention, the read/write unit performs the first and second de-interleaving operations as data is read from the memory buffer.