Abstract: A phase rotator generates an output signal having plurality of possible output phases with reduced phase jitter. The low jitter phase rotator includes a plurality of differential amplifiers configured to receive a plurality of input differential signals having different phases, and configured to generate a plurality of weighted signals responsive to the plurality of input differential signals. A plurality of digital-to-analog converters (DAC) are arranged into a plurality of groups, each group of DACs configured to provide current for one of the corresponding differential amplifiers. The number of active DACs in each group of DACs determines a relative weighting of the weighted signals, where relative weighting determining an output phase of an output signal of the phase rotator. The DACs are configured to adjust the output phase of the phase rotator. At a kth phase, N/4 adjacent DACs are activated that are indexed as m0, m1, . . . m((N/4)?1), wherein N is the number of said plurality of DACs.

Abstract: A scheme for PLL-based at-speed scan testing in which a clock generation circuit is used to generate different clock signals to scannable flip-flops of an integrated circuit. When the integrated circuit is under at-speed scan test mode of operation, the clock generation circuit receives a scan-clock signal to scan in a test vector to the scannable flip-flops during an input shift phase when shifting is enabled and to scan out a resultant vector from the scannable flip-flops during an output shift phase when shifting is also enabled. However, when shifting is not enabled during a capture phase between the two shift phases, the scan-clock signal triggers a 2-pulse circuit to release two pulses during the capture phase of at-speed scan testing. The two pulses from the 2-pulse circuit are based on an internal PLL-based clock signal. The clock generation circuit may be utilized in single or multiple clock domain systems.

Abstract: Satellite set-top boxes (STB) are increasingly being designed with multiple tuners, making them capable of receiving more than one program at a time. In addition, satellite STBs are increasingly being designed with multiple inputs, to permit reception of additional channels that will not fit within the conventional satellite intermediate frequency (IF) band (950-2150 MHz). Often, the STB must route these multiple inputs to the multiple tuners with some form of switching function, to allow each tuner to receive all channel bands. Accordingly, the invention includes an RFIC with two RF inputs and three RF outputs, and a crossbar switch that can route any input to any output. The two inputs are amplified by low-noise amplifier stages.

Abstract: Iterative code system for streaming hard disk drives (HDDs). A novel approach is presented by which any of a wide variety of error correcting codes can be applied within devices that include or interface to HDDs or other memory storage devices that provide streaming information. A means is provided by which at least two separate clock domains are employed such that the streaming information can be provided at a first rate according to a first clock domain, and the decoding processing of the streaming information can be provided at a second rate according to a second clock domain. Using this approach, a wide variety of error correcting codes can employed, including those whose decoding processing would not be possible if required to operate at the typically high rates at which streaming information is oftentimes provided from HDDs or other memory storage devices.

Abstract: An integrated circuit radio transceiver and method therefore includes a wireless access point that is operable to receive media content for subsequent delivery to at least one wireless mobile terminal and to store such media content until a specified delivery time or such media content is requested. The wireless access point is operable to generate transmissions of the media content at an increased power level either directly through attached point-to-point communications that span a super service area that overlaps service areas of other wireless access points or by way of broadcast transmissions at an increased power level that overlap the service areas of other wireless access points.

Abstract: A wireless access point wireless access point is operable to generate or update a history associated with a wireless terminal to facilitate the wireless access point making attachment decisions relating to the wireless terminal. The wireless access point is operable determine to remain attached to the wireless terminal or to form a second conclusion to prompt the wireless terminal and a second wireless access point to attach to each other. The first and second conclusions are based upon at least a partial history associated with the wireless terminal. The wireless access point also exchanges at least a portion of the history with another wireless access point and updates any stored history relating to the wireless terminal.

Abstract: A system for transmitting packets over a home network of communication channels, typically coax cable, including a set of nodes, at least one having a packet aggregation functionality in which the node forms an aggregation frame by aggregating one or more packets which have accumulated at the node and transmits the frame. A network coordinator coordinates access of the nodes to the channels. At least one node is operative to inform the coordinator when it has formed an aggregation frame comprising a plurality of packets and to provide the coordinator with comparison information comparing different transmission possibilities for the frame. The coordinator, preferably responsively, determines whether, when, and which of, the aggregated packets can be transmitted.

Abstract: A method for accurate signal detection begins by receiving a radio frequency signal, which is then converted into baseband signals. The processing then continues by performing a normalized auto correlation on the down-converted baseband signal to produce a normalized auto correlation signal. The process continues by performing a periodic pattern detection on the down-converted baseband signal to produce a normalized detected periodic signal. The process then continues by comparing the normalized auto correlation value with an auto correlation threshold and by comparing the normalized detected periodic signal with a set of thresholds. When the normalized auto correlation value compares favorably with the auto correlation threshold and when the normalized detected periodic signal compares favorably with the set of thresholds, the down-converted baseband signal is indicated to be a valid signal.

Abstract: An integrated circuit radio transceiver and method therefor includes circuitry and logic for transmitting outgoing or ingoing communication signals as well as one of a digital data signal or a digital clock on the same antenna signal paths between a radio and a switch fabric. The switch fabric is operable to selectively couple any of a plurality of antennas to antenna signal paths based upon the digital data and the digital clock extracted from at least one of the antenna signal paths conducting RF signals. The switch fabric is further operable to extract all required power from at least one antenna signal path that may be used to conduct RF.

Abstract: Methods and systems for minimizing distortions in an analog data signal include equalizing the analog data signal at a receive end. In an embodiment, the invention adapts equalization parameters to a signal path associated with the analog data signal. Adaptive control logic is implemented with analog and/or digital components. In an embodiment, the invention equalizes a discreet-time analog representation of an analog data signal. In an embodiment, the invention digitally controls equalization parameters. In an embodiment, a resultant equalized analog data signal is digitized. In an example implementation, an analog data signal is sampled, a quality of the samples is measured, and one or more equalization parameters are adjusted with digital controls as needed to minimize distortion of the samples. The equalized samples are then digitized. The present invention is suitable for lower rate analog data signals and multi-gigabit data rate analog signals.

Abstract: A system for transmitting packets over a network of communication channels, the system comprising a set of nodes comprising at least first and second nodes and a network access coordinator operative to coordinate the access of the set of nodes to a synchronous network of channels, wherein, if at least one individual packet has been transmitted from the first node to the second node which did not receive at least one packet, the second node is operative to send a retransmission request to the network access coordinator requesting retransmission of at least one individual packet.

Abstract: Methods and apparatus for calibrating a transitional loop, such as a phase locked loop, are disclosed. An example method includes performing an open loop calibration of a voltage controlled oscillator (VCO). The open loop calibration includes tuning the output oscillation frequency of the VCO to within a predetermined range of frequencies. The example method further includes determining a voltage offset and a gain error of an analog to digital converter (ADC) coupled with the phase locked loop. The example method also includes determining a gain offset of the open loop calibrated VCO using the voltage offset and the gain error of the ADC. In the example method, a signal provided by a charge pump of the PLL is adjusted based on the determined gain offset.

Abstract: A bandpass filter includes a plurality of resonators on a printed circuit board. An input pin is connected to a first resonator of the plurality of resonators. An output pin is connected to a second resonator of the plurality of resonators. The first and second resonators are magnetically coupled to each other. The first and second resonators are coupled to other resonators using mixed coupling. The other resonators are coupled to each other using electric coupling.

Abstract: A method of decompressing data words of an instruction set includes: A. filling a primary dictionary with at least one primary data word of the instruction set, each of the at least one primary data word being stored in the primary dictionary in a location associated with a distinct primary dictionary index; B. filling at least one secondary dictionary with at least one difference bit stream, each of the at least one difference bit stream being stored in one of the at least one secondary dictionary in a location associated with a distinct secondary dictionary index; C. receiving a code word, the code word comprising: a. a header which identifies the primary dictionary and a specific one of the at least one secondary dictionary; b. a first bit stream; and c. a second bit stream; wherein the first bit stream comprises the distinct primary dictionary index and the second bit stream comprises the distinct secondary dictionary index; D.

Abstract: The invention enables a gain adjustment in a receiver to improve signal quality by varying resistance of an input resistor array of a bandpass filter, the array having a plurality of resistors in series with switches that out of the path of the current when the resistors are in use.

Abstract: Methods and circuits utilizing a two stage adaptation algorithm to determine the optimal code for an equalizer to compensate a received signal is disclosed. In the first stage, a coarse tuning algorithm is used to choose a range of codes based on the amplitude of the received signal. The chosen codes will be used as reference points in the second stage. In the second stage, a fine tuning algorithm is used to select a code in the range of reference codes determined in stage one. The fine tuning algorithm looks to the status of the data lock signal generated by the clock recovery circuit. If the data lock signal does not indicate a lock, the fine tuning algorithm cycles through the range of reference codes. If the data lock signal indicates a lock, then that particular code is continued to be used for the equalizer.

Abstract: A computing device operates over a range of voltages and frequencies and over a range of processor usage levels. The computing device includes at least a variable frequency generator, a variable voltage power supply and voltage supply level and clocking frequency management circuitry. The variable frequency generator is coupled to the processor and delivers a clock signal to the processor. The variable voltage power supply is coupled to the processor and delivers voltage to the processor. The voltage supply level and clocking frequency management circuitry adjust both the voltage provided by the variable voltage power supply and the frequency of the signal provided by the variable frequency generator. The computing device includes a temperature sensor that provides signals indicative of the temperature of the processor and the voltage supply level and clocking frequency management circuitry adjusts the voltage and/or the clocking frequency provided by the variable voltage power supply.

Abstract: A method and system for monitoring and compensating the performance of an operational circuit is provided. The system includes one or more integrated circuit chips and a controller. Each integrated circuit chip includes one or more operational circuits, each operational circuit having at least one controllable circuit parameter. Each integrated circuit chip also includes a process monitor module at least partially constructed thereon. The controller is coupled to each process monitor module and to each operational circuit. The controller includes logic for evaluating the performance of an operational circuit based on data obtained from process monitor module and operational circuit related data stored in a memory. Based on the evaluation, the controller determines whether any deviations from desired or optimal performance of the circuit exist. If deviations exist, the controller generates a control signal to initiate adjustments to the operational circuit to compensate for the deviations.

Abstract: Methods and apparatus are provided for a cryptography accelerator to efficiently perform authentication and encryption operations. A data sequence is received at a cryptography accelerator. An encrypted authentication code and an encrypted data sequence is provided efficiently upon performing single pass authentication and encryption operations on the data sequence.

Abstract: A one-time programmable device includes a controller, a protection system, a static storage element and a latch, which can be referred to as a latch-based one-time programmable (OTP) element. In one example, the static storage element includes a thin gate-oxide that acts as a resistance element, which, depending on whether its blown, sets the latch into one of two states.