Abstract: A system and method for interrupt distribution in a multithread processor are disclosed. A connection between an interrupt and a set of thread processors can be programmed. When the interrupt is executed, the set of thread processors are affected. While executing the thread processor tasks, the connection may be reprogrammed to interrupt another set of thread processors.

Abstract: A process of maintaining access information between wireless hotspots is disclosed. A logon request from a wireless portable device is received by a first access point of a first wireless hotspot and use of the first access point by the wireless portable device is authenticated to establish an access session. Then, information related to the access session is passed to a shared register accessible by a plurality of wireless hotspots and the access session is monitored to determine whether a disconnect by the wireless portable device occurs. Additionally, when the wireless portable device moves from a coverage area of the first wireless hotspot to one coverage area of one of the plurality of wireless hotspots, the information related to the access session may be used to facilitate access to the one of the plurality of wireless hotspots by the wireless portable device.

Abstract: A switch, switched architecture and process for transferring data through an FCAL switch is disclosed. The switch uses multiple switch control circuits each coupled to one FCAL network and all connected to a crossbar switch. The switch control circuits are coupled together by a protocol bus for coordination purposes. Local conversations can occur on each FCAL loop and crossing conversations through the switch can occur concurrently. The OPN primitive is used to establish the connection before any data is transferred thereby eliminating the need for buffer memory in the switch control circuits. The destination address of each OPN is used to address a lookup table in each switch control circuit to determine if the destination node is local. If not, the destination is looked up and a connection request made on the protocol bus. If the remote port is not busy, it sends a reply which, causes both ports to establish a data path through the backplane crossbar switch.

Abstract: Apparatus, methods and systems for compensating for an I/Q imbalance may include compensating for an imbalance between a first component of a data signal and a second component of the data signal. The data signal may be modulated by a carrier signal having a frequency error. The first component may be characterized by at least one parameter. The method may include receiving the data and carrier signals; selecting a value for the parameter such that the frequency domain energy at negative frequencies is reduced; and modifying at least one of the components based on the value.

Abstract: A system and method for discovering channel impediments for Power over Ethernet (PoE) applications. Cabling power loss in PoE applications is related to the resistance of the cable itself. A PHY can be designed to measure electrical characteristics (e.g., insertion loss, cross talk, length, discontinuities, etc.) of the Ethernet cable to enable determination of the cable resistance. The determined resistance can be used in powering decisions and in adjusting power budgets allocated to power source equipment ports.

Abstract: An apparatus, method, and computer program for efficient rapid loss detection in a channel bonding system. A received packet having a packet sequence number (PSN) not equal to a next expected PSN is queued. A channel counter for a first channel on which the received packet was received is incremented. If all channel counters are non-zero, increment the next expected PSN to equal a lowest queued packet PSN. Forward the queued packet with the lowest queued packet PSN. Decrement a channel counter for a second channel from which the lowest PSN packet is forwarded.

Abstract: A phase locked loop (PLL) with small size and improved performance is achieved using a type 1 PLL, a frequency detector and logic for switching between the type 1 PLL and frequency detector. The logic disables the type 1 PLL and enables the frequency detector to bring the frequency of a PLL output signal to within a frequency locking range of the type 1 PLL, and then disables the frequency detector and enables the type 1 PLL to lock the phase of the PLL output signal.

Abstract: A communication system includes an integrated circuit (IC) die having an on-chip source termination. The on-chip source termination can be a non-precision resistor, such as an unsilicided poly resistor, or any other suitable termination. As compared to an off-chip source termination, the on-chip source termination can reduce voltage peaking and/or voltage overshoot in the IC die and/or at a load that is connected to the IC die. The IC die can further include a line driver to provide a source current. A bias generator can be included to provide a bias current to the line driver. The bias generator can include a first current source coupled to an off-chip resistor and a second current source coupled to an on-chip resistor. An output voltage of the IC die can be adjusted by manipulating a trim control of the off-chip resistor and/or a trim control of the on-chip resistor.

Abstract: A hand held radio host includes circuitry for selectively providing power to radiating transceiver elements and non-radiating application elements according to a plurality of power modes of operation to achieve desired effects and in a way that saves power and extends battery life. In one embodiment of the invention, the hand held host operates in one of three modes. In a full power mode, any selected application element, as well as all transceiver elements, are powered on at the same time. Thus, for example, a cell phone module, a wireless personal access network module, a wireless local area network module, and one of a pager/short message service message module may all be powered on at the same time to receive corresponding messages, calls, data sessions, etc.

Abstract: Turbo decoder employing ARP (almost regular permutation) interleave and inverse thereof as de-interleave. A novel means is presented herein by which a common module can perform both ARP interleaving and ARP de-interleaving during turbo decoding processing. A novel approach is presented that allows a common structure to perform both the interleaving and de-interleaving operations. In some embodiments, certain ARP interleaving parameters are processed to generate ARP de-interleaving parameters. In even other embodiments, certain ARP interleaving parameters are processed to generate an algebraic, closed form ARP de-interleaver function that can be employed during turbo decoding processing. This novel approach obviates the need for extremely large pre-computed look-up-tables. Moreover, this novel approach can accommodate many different interleaves and information block sizes with very little overhead.

Abstract: A method and apparatus is disclosed for an internal control circuit that switches transistors rapidly on and off to stabilize the output voltage or current of a switch-mode power supply (SMPS). The internal control circuit uses analog and digital signals to regulate the output voltage of the switch-mode power supply. The internal control circuit adjusts the output voltage using pulse width modulation. The duty cycle of the pulse is based upon the comparison of the output voltage and a reference level.

Abstract: A high-speed serial demultiplexer receives over four high-speed serial data lines at a nominal rate of 10 GBPS and demultiplexes the data to 16 lines with a rate of 2.5 GHz each. The demultiplexer circuits are configured as two D type latches, one of which latches data on the positive edge of a 5 GHz clock, the other of which latches every other bit of the 10 GBPS data on the negative edge of the 5 GHz clock, alternating with the first D latch. Each of the two D latches is configured as a master-slave flip-flop that includes a master D latch and a slave D latch. The master receives the data at the 10 GBPS rate and clocks every other bit to its output using an edge of the 5 GHz clock (the positive edge for one of the D-latches, the negative for the other). The slave clocks the data form the master to its output on the opposite edge of the clock following the master.

Abstract: Directly computing Feed Forward Equalizer (FFE) coefficients and Feed Back Equalizer (FBE) coefficients of a Decision Feedback Equalizer (DFE) from a channel estimate. The FBE coefficients have an energy constraint. A recursive least squares problem is formulated based upon the DFE configuration, the channel estimate, and the FBE energy constraint. The recursive least squares problem is solved to yield the FFE coefficients. The FFE coefficients are convolved with a convolution matrix that is based upon the channel estimate to yield the FBE coefficients. A solution to the recursive least squares problem is interpreted as a Kalman gain vector. A Kalman gain vector solution to the recursive least squares problem may be determined using a Fast Transversal Filter (FTF) algorithm.

Abstract: The computational load imposed by communications software executed on a general purpose processor can be significantly reduced by exploiting periods during an active connection when no data is being received. In particular, execution of many receive path signal processing algorithms can be disabled when no data is being received. The transmit path continues output modulation as with a normal connection, so as to trick a remote communications device into believing the connection is still normal. However, substantial portions of the local receive path can be disabled, thereby reducing computational load on the general purpose processor and freeing additional compute cycles for application and/or operating system program use.

Abstract: Aspects of the invention provide a system for a mixed analog-digital automatic gain control. The received analog signal is amplified by the analog amplifier and then converted to a digital value by an ADC. A clamp reference level of the converted signal is removed prior to applying a digital gain to a digital multiplied. Once the digital gain is applied, the clamp reference level is restored to the digital signal. A loop filter determines the system time response from the error between an amplitude parameter of the received signal and an AGC reference level. A gain separation circuit generates the system gain and separates it into a digital gain and an analog gain in a way to maximize the use of the analog amplifier. The analog gain is applied to the analog amplifier and the digital gain is applied to the digital multiplier.

Abstract: A P-type metal oxide semiconductor (PMOS) device can include an N-well that does not extend completely throughout the active region of the PMOS device. For example, the PMOS device can be fabricated using a masking step to provide an N-well having an inner perimeter and an outer perimeter. The inner perimeter of the N-well surrounds at least a portion of the active region of the PMOS device. According to an embodiment, the inner perimeter of the N-well surrounds the entire active region. The PMOS device can include a deep N-well in contact with the N-well.

Abstract: LDPC (Low Density Parity Check) coded modulation hybrid decoding using non-Gray code maps for improved performance. Check node updating and symbol node updating are successively and alternatively performed on bit edge messages for a predetermined number of decoding iterations or until sufficient degree of precision is achieved. The symbol node updating of the bit edge messages uses symbol metrics corresponding to the symbol being decoded and the bit edge messages most recently updated by check node updating. The check node updating of the bit edge messages uses the bit edge messages most recently updated by symbol node updating. The symbol node updating computes possible soft symbol estimates. LDPC coded modulation hybrid decoding can decode an LDPC-BICM (Low Density Parity Check-Bit Interleaved Coded Modulation) signal having a symbol mapped using non-Gray code mapping. By using the non-Gray code mapping, a performance improvement is achieved over an only Gray code mapping system.

Abstract: Fast min*? (min-star-minus) or max*? (max-star-minus) circuit in LDPC (Low Density Parity Check) decoder. A novel and efficient approach by which certain of the calculations required to perform check node processing within various types of decoders is presented. The functionality and architectures presented herein are applicable to LDPC decoders and may also be employed within other types of decoders that are operable to decode other types of coded signals as well. The parallel and sometimes simultaneous calculation and determination of certain parts of the overall resultant of the max*? and/or min*? processing allows for very fast operation when compared to prior art approaches.

Abstract: IPHD (Iterative Parallel Hybrid Decoding) of various MLC (Multi-Level Code) signals. Various embodiments are provided by which IPHD may be performed on MLC LDPC (Multi-Level Code Low Density Parity Check) coded modulation signals mapped using a plurality of mappings. This IPHD may also be performed on MLC LDPC coded modulation signals mapped using only a singe mapping as well. In addition, various embodiments are provided by which IPHD may be performed on ML TC (Multi-Level Turbo Code) signals. These principles of IPHD, shown with respect to various embodiments IPHD of MLC LDPC coded modulation signals as well as the IPHD of ML TC signals, may be extended to performing IPHD of other signal types as well. Generally speaking, based on the degree of the MLC signal, a corresponding number of parallel paths operate in cooperation to decode the various levels of the MLC signal.

Abstract: According to one exemplary embodiment, a synchronous power gauge is coupled to a processor for determining total charge consumed from a power source in an electronic device. The synchronous power gauge includes a controller for receiving a synch signal that indicates whether the electronic device is in an operating power mode or a low power mode. The synchronous power gauge further includes an analog to digital converter controlled by the controller and is configured to process a signal associated with current drawn from the power source when the electronic device is in the operating power mode. An accumulator coupled to the analog to digital converter maintains and updates a sum of digital outputs provided by the analog to digital converter when the electronic device is in the operating power mode. The processor uses the sum of digital outputs to determine the total charge consumed from the power source.