Abstract: A transistor driver circuit with a plurality of transistors, each having source and drain regions formed in a substrate. At least first and second interconnect layers are formed on top of the substrate. A first plurality of contacts connect the source regions to one of the first or second interconnect layers. A second plurality of contacts connect the drain regions to the other of the first or second interconnect layers. The first and second interconnect layers cover a region above the substrate area in which the plurality of transistors reside so as to achieve a low ohmic result. The second interconnect layer has openings therein for one of the respective first or second plurality of contacts to pass therethrough and couple to the at least one first interconnect layer. Either the first or second interconnect layers can function as an input or output for the circuit.

Abstract: A method for dynamically regulating the power consumption of a high-speed integrated circuit which includes a multiplicity of processing blocks. A first metric and a second metric, which are respectively related to a first performance parameter and a second performance parameter of the integrated circuit, are defined. The first metric is set at a pre-defined value. Selected blocks of the multiplicity of processing blocks are disabled in accordance with a set of pre-determined patterns. The second metric is evaluated, while the disabling operation is being performed, to generate a range of values of the second metric. Each of the values corresponds to the pre-defined value of the first metric. A most desirable value of the second metric is determined from the range of values and is matched to a corresponding pre-determined pattern. The integrated circuit is subsequently operated with selected processing blocks disabled in accordance with the matching pre-determined pattern.

Abstract: Bandwidth efficient coded modulation scheme based on MLC (Multi-Level Code) signals having multiple maps. The use of multiple maps is adapted to various types of coded signals including multi-level LDPC coded modulation signals and other MLC signals to provide for a significant performance gain in the continual effort trying to reach towards Shannon's limit. In the instance of LDPC coded signals, various level LDPC codewords (e.g., an MLC block) are generated from individual corresponding LDPC encoders. These various level LDPC codewords are arranged into a number of sub-blocks that corporately form an MLC block. Encoded bits from levels of the MLC block are arranged to form symbols that are mapped according to at least two modulations. Each modulation includes a constellation shape and a corresponding mapping. This use of multiple mappings provides for improved performance when compared to encoders that employ only a single mapping.

Abstract: A Radio Frequency (RF) structure services an antenna having a characteristic impedance and includes a differential Power Amplifier (PA), a differential Low Noise Amplifier (LNA), and a balun transformer. The differential PA has a differential PA output with a PA differential output impedance. The differential LNA has a differential LNA input with an LNA differential input impedance. The balun transformer has a singled ended winding coupled to the antenna, a differential winding having a first pair of tap connections coupled to the differential PA output and a second pair of tap connections coupled to the differential LNA input, and a turns ratio of the single ended winding and the differential winding. The turns ratio and the first pair of tap connections impedance match the PA differential output impedance to the characteristic impedance of the antenna. The turns ratio and the second pair of tap connections impedance match the LNA differential input impedance to the characteristic impedance of the antenna.

Abstract: A radio transceiver includes circuitry that enables received RF signals to be down-converted to baseband frequencies and baseband signals to be up-converted to RF signals prior to transmission without requiring conversion to an intermediate frequency. The circuitry includes a temperature sensing module that produces accurate voltage level readings that may be mapped into corresponding temperature values. A processor, among other actions, adjusts gain level settings based upon detected temperature values. One aspect of the present invention further includes repetitively inverting voltage signals across a pair of semiconductor devices being used as temperature sensors to remove a common mode signal to produce an actual temperature-voltage curve. In one embodiment of the invention, the circuitry further includes a pair of amplifiers to facilitate setting a slope of the voltage-temperature curve.

Abstract: A wireless human interface device (HID) includes an input interface module for accepting inputs from a user; a microprocessor for processing the accepted inputs; a wireless transmitter for transmitting the accepted inputs to a host; and a temperature sensor for determining the temperature of the wireless HID, wherein the microprocessor transmits the sensed temperature via the wireless transmitter to the host for displaying.

Abstract: Methods and apparatus are provided for making function calls to various cryptography accelerators. An application program interface abstraction layer coupled to a cryptography accelerator receives generic function calls from designer configured software and performs operations such as security association management, policy management, packet processing, cryptography accelerator configuration, and key commit management. Upon receiving a generic function call, the abstraction layer performs processing to make a chip specific function call or update abstraction layer management information associated with the generic function call.

Abstract: An interleaving operation can scramble (permute) a data stream, or each dimension (set of symbols (a, b, c, . . . )) in a data stream, immediately following FEC encoding or dimension multiplexing of the data stream. Bursts of errors might be combined with the permuted data before, during, or after transmission. A de-interleaver reorders the received symbols and, in the process, spreads (separates) the bursts of errors. Also, using the multi-dimensional interleaving and de-interleaving can balance SNR on each channel. Spreading the errors and/or balancing SNR can keep bursts from overwhelming the FEC decoder or an FEC decoder in any one channel. In one example, interleaving and de-interleaving can be used to scramble data over Ethernet twisted wire pairs. In another example, interleaving and de-interleaving can be used to scramble data or information broadcast via wireless telecommunications channels (e.g., radio frequency channels, multi-antenna channels, etc).

Abstract: A technique to determine sampling frequency offset (SFO) phase shift and perform channel estimation for symbols of a signal communicated across a multiple-input-multiple-output (MIMO) communication channel, in which preambles utilized for channel estimation are sent over more than one time block. Because the transmission of preambles used for channel estimation are sent over multiple time blocks, a SFO phase shift that is linear across tones of an OFDM signal is experienced between preambles of the two time blocks. Upon detection of the SFO phase shift, a weighting matrix used for channel estimation is modified to account for the SFO phase shift, in order to perform the channel estimation with correction for the SFO phase shift.

Abstract: In a method of automatically identifying a format of a video signal, where the video signal includes HSync pulses, VSync pulses, and video display data, the video signal is received, information about timing and width characteristics of the HSync pulses and the VSync pulses is extracted from the video signal, and the format of the video signal is determined based on the extracted information.

Abstract: High precision continuous time gmC BPF (Band Pass Filter) tuning. A novel approach is presented by which a continuous time signal serves as a BPF control voltage for tuning of a BPF within a communication device (e.g., transceiver or receiver). A PLL (Phase Locked Loop) tunes the center frequency of the BPF using this continuous time signal, and the PLL oscillates at the center frequency of the BPF. The BPF is implemented as a gmC (transconductance-capacitance) filter, and the PLL is implemented using a number of gm (transconductance) cells as well. The PLL's gm cells and the BPF's gm cells are substantially identical in form. All of these gm cells are operated within their respective linear regions. This similarity of gm cells within the PLL and the BPF provide for substantial immunity to environmental perturbations including temperature and humidity changes as well as fluctuations of power supply voltages.

Abstract: A system and method are used to allow high speed communication between a circuit and an external device. The system and method include a PLL with multiple phased outputs configured to be controlled digitally, a deskew PLL configured to align a clock of controller circuitry to interface circuitry, and a phase interpolated voltage controlled delay line configured to phase shift incoming signals. Analog design techniques of phase interpolation accurately position clocks and strobe signals that are required for high speed interfaces. The high speed interface is for transmitting and receiving signals from the external device, for example, a DDR DRAM.

Abstract: A radio frequency (RF) phase shifter having an RC-CR circuit that includes a first capacitor having a first capacitor node and a second capacitor node and a first resistor coupled between the first capacitor node and a ground. The RC-CR circuit also includes a second resistor having a first resistor node and a second resistor node and a second capacitor coupled between the first resistor node and the ground. The RF phase shifter generates arbitrary phase shift by using a scheme of adding two perpendicular vectors with variable gains (or amplitudes).

Abstract: A technique to estimate phase noise across a multiple-input-multiple-output (MIMO) communication channel, in which phase noise estimation is obtained by solving a matrix equation that has more unknowns than available equations. Once the phase noise estimate is determined, appropriate phase correction is applied to correct for phase noise induced errors in the received signal.

Abstract: A technique to determine carrier frequency offset (CFO) phase shift and perform channel estimation for symbols of a signal communicated across a multiple-input-multiple-output (MIMO) communication channel, in which preambles utilized for channel estimation are sent over more than one time block. Because the transmission of preambles used for channel estimation are sent over multiple time blocks, a CFO phase shift that is flat across tones of an OFDM signal is experienced between preambles of the two time blocks. Upon detection of the CFO phase shift, a weighting matrix used for channel estimation is modified to account for the CFO phase shift, in order to perform the channel estimation with correction for the CFO phase shift.

Abstract: Turbo decoder employing ARP (almost regular permutation) interleave and arbitrary number of decoding processors. A novel approach is presented herein by which an arbitrarily selected number (M) of decoding processors (e.g., a plurality of parallel implemented turbo decoders) be employed to perform decoding of a turbo coded signal while still using a selected embodiment of an ARP (almost regular permutation) interleave. The desired number of decoding processors is selected, and very slight modification of an information block (thereby generating a virtual information block) is made to accommodate that virtual information block across all of the decoding processors during all decoding cycles except some dummy decoding cycles. In addition, contention-free memory mapping is provided between the decoding processors (e.g., a plurality of turbo decoders) and memory banks (e.g., a plurality of memories).

Abstract: A Radio Frequency (RF) structure services an antenna having a characteristic impedance and includes a differential Power Amplifier (PA), a differential Low Noise Amplifier (LNA), and a balun transformer. The differential PA has a differential PA output with a PA differential output impedance. The differential LNA has a differential LNA input with an LNA differential input impedance. The balun transformer has a singled ended winding coupled to the antenna, a differential winding having a first pair of tap connections coupled to the differential PA output and a second pair of tap connections coupled to the differential LNA input, and a turns ratio of the single ended winding and the differential winding. The turns ratio and the first pair of tap connections impedance match the PA differential output impedance to the characteristic impedance of the antenna. The turns ratio and the second pair of tap connections impedance match the LNA differential input impedance to the characteristic impedance of the antenna.

Abstract: A DSP based SERDES performs compensation operations to support high speed de-serialization. A receiver section of the DSP based SERDES includes one or more ADCs and DSPs. The ADC operates to sample (modulated) analog serial data and to produce digitized serial data (digital representation of the modulated analog serial data). The DSP communicatively couples to the ADC and receives the digitized serial data. Based upon the known characteristics of the digitized serial data and the digitized serial data itself, the DSP determines compensation operations to be performed upon the serial data to compensate for inadequacies of the receiver and/or channel response. These compensation operations may be (1) performed on the analog serial data before digitization by the ADC; (2) applied to the ADC to modify the operation of the ADC; and/or (3) performed on the digitized serial data by the DSP or another device.

Abstract: A system for implementing Incremental Redundancy (IR) operations in a wireless receiver includes a baseband processor, an equalizer, a system processor, and an IR processing module. The baseband processor receives an analog signal corresponding to a data block and samples the analog signal to produce samples. The equalizer receives the samples from the baseband processor, equalizes the samples, and produces soft decision bits corresponding to the data block. The equalizer may be implemented as a distinct processing component or may be performed by the baseband processor or system processor. The system processor receives at least the soft decision bits and initiates IR operations. The IR processing module receives the soft decision bits of the data block and performs IR operations on the data block in an attempt to correctly decode a corresponding data block.

Abstract: A method and system for measuring noise of an on-chip power supply. In an embodiment, the system comprises a delay line that receives as an input a signal such as a square wave. The delay line may comprise a series of inverters connected to the power supply. The output of the delay line may combine the input signal and the noise signal from the power supply to produce a series of delayed versions of the input signal. Analysis of the output signal yields characteristics associated with the noise signal of the power supply such as its spectrum. In another embodiment, the system may comprise at least one mixer that modulates an input signal, such as a sinusoid, with the noise signal of the power supply. Demodulating the mixed signal then yields the noise signal of the power supply for further analysis.