Abstract: A system and method is provided for interleaving data in a communication device. The system includes a memory that stores blocks of data to be interleaved. In addition to the memory, the system includes a write module and a read module, each of which is coupled to the memory. The write module is configured to receive a burst of data and write blocks of data from the burst into the memory. The write module is also configured to provide control information to the read logic. The control information includes a rolling burst counter and a burst profile bank identifier for each block. If interleaving is activated, the control information also includes information pertaining to how the read module should interleave the block. If interleaving is not activated, the control information also includes the byte length size of the burst. The read module reads blocks of data from memory in either an interleaved fashion or a non-interleaved fashion in accordance with the control information.

Abstract: A system and method for bad weave detection for inverse telecine. To detect a bad weave artifact, the number of reversals of the difference polarity between successive lines within a column of samples is counted. The count of the number of reversals of the difference polarity is referred to as the polarity change count. In the execution phase, the polarity change count can be used by a bad weave detector to take a system out of lock. The polarity change count can also be used during the detection phase to detect a particular cadence.

Abstract: A media access controller (MAC) is configured with a header creator circuit. The header creator circuit is configured with logic for receiving a data packet and determining whether the received data packet has an existing packet header prepended thereto. The header creator circuit is further configured to determine if the length of the received data packet includes a cyclic redundancy code. Still further, the header creator circuit is configured to determine a packet header length field value for the received data packet. If the header creator circuit determines that a cyclic redundancy code needs to be included with the received data packet, then the header creator circuit is able to generate a CRC flag. If the data packet needs to be encrypted, then the header creator circuit will generate an encryption flag if it is determined that the received data packet should be encrypted. Finally, the header creator circuit generates a packet header having a plurality of fields.

Abstract: Tail-biting turbo code for arbitrary number of information bits. A novel means is presented in which, for most cases, no extra symbols at all need to be padded to an input sequence to ensure that a turbo encoder operates according to tail-biting (i.e., where the beginning and ending state of the turbo encoder is the same). In a worst case scenario, only a single symbol (or a single bit) needs to be padded to the input sequence. Herein, all of the input bits of the input sequence are interleaved within the turbo encoding. In the instance where the at most one symbol (or at most one bit) needs to be padded to the input sequence, then that at most one symbol (or one bit) is also interleaved within the turbo encoding. Moreover, any size of an input sequence can be accommodated using the means herein to achieve tail-biting.

Abstract: A voltage interpolation circuit includes a resistive ladder connected between ground and a voltage input and having a plurality of resistors with voltage taps between the resistors. An amplifier (optionally) has first and second capacitors connected together at their respective first terminals and to an input of the amplifier. A first plurality of switches connect respective taps to a second terminal of the first capacitor. A second plurality of switches connect the respective taps to a second terminal of the second capacitor. An output voltage is interpolated by controlling the first and second pluralities of switches.

Abstract: A system and method for producing a family of power modules having a common footprint that enables the customer to flexibly choose a power module size without incurring the costs of a relayout of a system design. In one embodiment, the power modules are directed to a point-of-load power controllers.

Abstract: A data synchronizer is provided for synchronizing data across two different clock domains in a manner that avoids additive jitter. The data synchronizer includes a synchronizer inputting a sampling clock and a data clock, and outputting an edge pulse. A synchronizer jitter lockout circuit inputs the edge pulse and the sampling clock and outputs a data sampling enable signal which never coincides with a data transition.

Abstract: The present invention relates to frequency dividers. The frequency divider comprises an input, a counter, a first comparator, an interconnect, and an output. The counter has a counter reset port and is configured to receive a clock signal from the input and to produce a sum signal. The first comparator is configured to receive the sum signal, to compare the sum signal to a first integer, and to produce a first comparison signal. The interconnect is configured to convey the first comparison signal from the first comparator to the counter reset port. The output coupled to the first comparator. The clock signal has a periodic waveform. The sum signal represents a first sum, which equals a number of waveforms of the clock signal received by the counter after the counter has been reset. In a first embodiment, the first integer is selectable from a set of at least three consecutive integers. In a second embodiment, a frequency of the clock signal is at least 1.5 gigahertz.

Abstract: A method of providing for synchronizing one or more synchronous terminals with one or more synchronous endpoints, each synchronous terminal and each synchronous endpoint having an asynchronous communications network coupled between at least one synchronous terminal and at least one synchronous endpoint. A synchronization protocol is established between a synchronous terminal and a synchronous end point by providing a gateway between the asynchronous communications network and the synchronous end point, the gateway communicating with the synchronous terminal over the asynchronous communications network in accordance with the synchronization protocol. The synchronization protocol includes sending a message from the gateway to the synchronous terminal, the message containing a timestamp identifying a clock associated with the synchronous end point.

Abstract: According to one exemplary embodiment, an amplitude compensation circuit includes a first composite programmable buffer for receiving a first input signal with a first input amplitude. The amplitude compensation circuit further includes a second composite programmable buffer for receiving a second input signal with a second input amplitude. The amplitude compensation circuit also includes a feedback circuit coupled to respective outputs of the first and second composite programmable buffers. According to this embodiment, the feedback circuit compares a first output amplitude of the first composite programmable buffer with a reference voltage and a second output amplitude of the second composite programmable buffer with the reference voltage and provides first and second control signals for adjusting the respective gains of the first and second composite programmable buffers so as to reduce respective differences between the first and second output amplitudes and the reference voltage.

Abstract: The present invention provides a simultaneous switching (SS) test mode. SS test modules supporting an SS test mode are provided. When SS test mode is enabled, SS test mode data is driven on a data bus during an idle bus period. Otherwise, when SS test mode is disabled, no SS test mode data is driven on a data bus during an idle bus period.

Abstract: Interleaver for iterative decoder. A memory management scheme allows for single plane/single port memory devices to be used by the interleaver. The design is adaptable to soft-in soft-out (SISO) decoders that perform iterative decoding. The interleaver may be implemented within communication devices that implement two distinct SISOs that operate cooperatively or within communication devices that employ a single SISO (in a recycled embodiment) that functionally performs the analogous decoding operations that would be performed by the two distinct SISO implementation. The use of single plane/single port memory devices by the interleaver allows for a great deal of savings from many perspectives: the sizes of the required interleaver memory and the interleaver pattern memory are both cut in half using this approach, and a cost savings may also be realized, in that, cheaper, slower memories may be used since each respective interleaver memory is read only every other cycle.

Abstract: In a transceiver system a passband single carrier transmitter is coupled to a first ultra-wide-band wireless transmission channel and a receiver may be coupled to the ultra-wide-band wireless transmission channel. The receiver may receive signals transmitted by the passband single carrier transmitter over the ultra-wide-band wireless transmission channel at a baud rate less than or equal to half of a spectral bandwidth of the signal transmitted by the passband single carrier transmitter. A passband single carrier transmitter may transmit a symbol stream via lossy ultra-wide-band wireless transmission channel at an adaptively chosen baud rate that is based on the lossy ultra-wide-band wireless transmission channel. The adaptively chosen baud rate may vary over a range that includes baud rates less than or equal to half of a spectral bandwidth of the transmitted symbol stream. A receiver may receive the transmitted symbol stream from the lossy ultra-wide-band wireless transmission channel.

Abstract: Inverse function of min*:min*? (inverse function of max*:max*?). Two new parameters are employed to provide for much improved decoding processing for codes that involve the determination of a log corrected minimal and/or a log corrected maximal value from among a number of possible values. Examples of some of the codes that may benefit from the improved decoding processing provided by the inverse function of min*:min*? (and/or inverse function of max*:max*?) include turbo coding, parallel concatenated trellis coded modulated (PC-TCM) code, turbo trellis coded modulated (TTCM) code, and low density parity check (LDPC) code among other types of codes. The total number of processing steps employed within the decoding of a signal is significantly reduced be employing the inverse function of min*:min*? (and/or inverse function of max*:max*?) processing.

Abstract: Presented herein are systems and methods for two address map for transactions between an X-bit processor and a Y-bit wide memory. A processor subsystem comprises a first address space, a second address space, and a bridge. The first address space stores data words of a first length. The second address space stores data words of a second length. The bridge performs one transaction after receiving a transaction with an address corresponding to the first address space and performs two transactions after receiving a transaction with the address corresponding to the second address space.

Abstract: Enhanced DOCSIS upstream channel changes. A CMTS directs channel changing of a CM, sometimes between upstream data bursts. Logical channels, part of a single frequency channel, may be used, and the channel changing may be performed between those logical channels. Multiple upstream burst profiles and/or modulation densities may be used providing high degrees of robustness, fidelity, and throughput and allowing great channel flexibility. A CM may be switched between channels without losing transmitter capability. Even if some throughput rate may be sacrificed during the channel changing, the CM will still be able to continue data throughput. Then, the new channel may then undergo the initialization and ranging processes thereby enabling greater throughput on that new channel. After undergoing the initialization and ranging processes, the new channel will then be a fully equivalent member of the CM communication system.

Abstract: A padring formed on a semi conductive substrate die provides Electro Static Discharge (ESD) protection for a Radio Frequency (RF) circuit also formed on the semi conductive substrate die. The padring includes a voltage supply rail, a ground rail, a plurality of signal pad structures, and a plurality of voltage clamps. The plurality of signal pad structures are disposed between the voltage supply rail and the ground rail. Each signal pad structure includes a signal pad that couples to the RF circuit, a voltage supply path diode disposed between and coupled between the signal pad and the voltage supply rail, and a ground path diode disposed between and coupled between the signal pad and the voltage supply rail. The plurality of voltage clamps are disposed between and coupled between the voltage supply rail and the ground rail.

Abstract: In a method and system for component sync detection and alignment, the Y/G channel is used as a master channel from which the vertical and the horizontal syncs are detected by a master sync generator. The master sync generator determines a fast and slow slice level for generating a rough and a fractional detection of the vertical sync and the horizontal sync and also generates a master sync timing window signal. A slave sync generator aligns the Pb/B and Pr/R channels to the Y/G channel by making use of the vertical, horizontal, and timing window sync signals produced by the master sync generator and by generating a slave slice level to detect the vertical and horizontal syncs in the slave channels. Positional differences in the alignment between the master channel and the slave channels are determined and stored for use in subsequent frame alignment.

Abstract: A method, system, and computer program product for receiving and resequencing a plurality of data segments received on a plurality of channels of a bonding channel set, comprising determining if a sequence number of a received segment matches an expected sequence number. If so, the process includes forwarding the segment for further processing, incrementing the expected sequence number; and forwarding any queued packets corresponding to the expected sequence number and immediately succeeding sequence numbers less than a sequence number of annexed missing segment. If the sequence number of the received segment does not match the expected sequence number, the received segment is queued at a memory location. The address of this location is converted to a segment index. The segment index is stored in a sparse array.

Abstract: A fractal antenna array based on a modified Peano-Gosper curve. The fractal antenna array is constructed using a 100-segment fractal curve that has the fractal expansion in a linear direction.