Abstract: An downstream external Physical Layer (PHY) interface between a network and an edge quadrature amplitude modulator (EQAM) is provided. The interface comprises, an input direct memory access (DMA) controller enabled to control rate of packets received from the network, a plurality of buffers to store received packets, a first module enabled to convert packets to a first format and a second module enabled to convert packets to a second format. The interface further comprises a plurality of processors enabled to customize an output format of packets based on instructions stored in an instruction memory and a plurality of flow meters enabled to determine an output rate for packets based on, at least in part, a modulator rate of the EQAM. An output DMA controller controls the rate of egress of packets to the EQAM.

Abstract: A system and method for communicating information using Layer 1 from a powered device to power source equipment via Ethernet. In one embodiment, Layer 1 information such as power management, classification, temperature, and disconnect information is transmitted from a powered device to power source equipment using an AC signal that has a cycle defining a first time period during which the AC signal is turned on and a second time period during which the AC signal is turned off. A type of information being sent by the powered device can be determined based on characteristic on/off times of the AC signal cycle.

Abstract: A system performs automated at-speed testing of a plurality of devices that generate serial data signals having multiple gigabit per second baud rates. The system includes a test head including a device interface board (DIB), the DIB having a device under test holding device for coupling the devices to the DIB. The system also includes a rider board including a multiplexing system coupled to a control system and to the DIB, the rider board being configured to route a serial data test signal having multi-gigabit per second baud rate through one or more of the devices.

Abstract: A receiver portion includes a bandpass filter (e.g. SAW filter) that performs channel selection from an input signal having a plurality of channels, and an image cancellation circuit that is in parallel with the bandpass filter. The bandpass filter performs channel selection to select a desired channel that falls in a passband of the bandpass filter. Since the passband is typically a few channels wide, the image channel falls outside the passband and is attenuated by the stopband attenuation of the bandpass filter. The image cancellation circuit includes an attenuator and a phase shifter. The attenuator is configured to have the same attenuation as the stopband attenuation of the bandpass filter at the image channel frequency, and phase shifter is configured to provide a phase shift of approximately 180 degrees. Therefore, the image cancellation circuit has an output that is equal in amplitude, but opposite in phase, to that of the bandpass filter at the image channel frequency.

Abstract: Current-controlled CMOS (C3MOS) wideband input data amplifier for reduced differential and common-mode reflection. Impedance matching and bandwidth extension provides desired gain at higher frequencies and may be achieved at the interface between silicon and package and/or circuit board within various integrated circuits that may be employed within communication devices. In some instances, a differential transistor pair is employed that also includes Miller capacitors coupled between the gate of one transistor of the differential transistor pair to the drain of the other transistor of the differential transistor pair. This can also include series load connected resistors and inductors coupled between the respective drains of the transistors of the differential transistor pair to a power supply voltage. Also, series connected input inductors may also couple to the gates of the transistors of the differential transistor pair.

Abstract: Certain embodiments of the invention provide a method and system for TERC4 decoding using minimum distance rule. A plurality of bits may be received that may indicate addresses of samples of data. A lookup table may be generated based on the received plurality of bits to determine corresponding output samples of data. The received plurality of bits may be exclusive ORed with the generated corresponding output samples of data. A distance value for each sample of data may be calculated based on an output generated by the exclusive ORing of the received plurality of bits with the generated corresponding output samples of data. An error in each of the received samples of data may be corrected based on the calculated distance value.

Abstract: Certain aspects of a method for reducing noise disturbing at least one signal in an electronic device may comprise shielding a first layer doped with a first dopant from a signaling layer employing a second layer doped with a second dopant. A first signaling component of the signaling layer may be coupled to the second layer and a second signaling component of the signaling layer may be coupled to the second layer. The second layer may be coupled to the first layer, and this reduces the signal disturbing noise in the electronic device. Shielding the first layer from the signaling layer may comprise disposing the second layer between the first layer and the signaling layer. Shielding the first layer from the signaling layer may comprise disposing a deep N-well between the first layer and the signaling layer.

Abstract: Aspects of a method and system for digital to analog conversion for power amplifier driver amplitude modulation are presented. Various aspects of the system may include circuitry that enables oversampling, within a single integrated circuit device, of each of a plurality of samples in a digital baseband signal. The circuitry may enable reduction of a number of bits, i.e., coarse quantization, in each of the oversampled plurality of samples so as to cause displacement of the quantization noise that occurred as a result of the coarse quantization. A subsequent signal may be generated based on the oversampled signal. The circuitry may enable the subsequent signal to be low-pass filtered utilizing filter circuitry in the single integrated circuit device, thereby attenuating the quantization noise displaced into the higher frequency range of the oversampled signal.

Abstract: A switch, switched architecture and process for transferring data through an FCAL switch is disclosed. The switch uses multiple switch control circuits each coupled to one FCAL network and all connected to a crossbar switch. The switch control circuits are coupled together by a protocol bus for coordination purposes. Local conversations can occur on each FCAL loop and crossing conversations through the switch can occur concurrently. The OPN primitive is used to establish the connection before any data is transferred thereby eliminating the need for buffer memory in the switch control circuits. The destination address of each OPN is used to address a lookup table in each switch control circuit to determine if the destination node is local. If not, the destination is looked up and a connection request made on the protocol bus. If the remote port is not busy, it sends a reply which causes both ports to establish a data path through the backplane crossbar switch.

Abstract: Multi-band single-carrier modulation. A novel approach is presented by which interference compensation may be performed for signals received by a piconet operable device. The piconet operable device may be implemented within a region that includes two or more SOPs (Simultaneously Operating Piconets). Estimation of the level and location of interference is performed and the input to a decoder (within the piconet operable device) is selectively weighted to ensure that the effect of any existent interference within the signal received by the piconet operable device is minimized. Different interference levels are dealt with differently. For one example, portions of the received signal having undergone a large amount of interference may be simply treated as erasures with respect to the input the decoder. For another example, portions of the received signal having undergone some smaller degree of interference, but some interference nonetheless, may be de-weighted before being provided to the decoder.

Abstract: A method of optimizing a communication system for receiving and processing an input communication signal includes selecting a first noise margin m to be applied against an external noise present on the input communication signal. The method further includes selecting a second noise margin mi to be applied against an internal noise introduced on the communications signal by the communication system. The second noise margin is a predetermined function of the first noise margin. The method also includes calculating a virtual noise to signal ratio that is a combination of an external noise to signal ratio NSRe, an internal noise to signal ratio NSRi, the first noise margin and the second noise margin. The method further includes adjusting one or more system parameters so as to maintain the virtual noise to signal ratio at a predetermined margin above a required noise to signal ratio.

Abstract: A multiplexing scheme to select either an I component or a Q component for input to I channel and Q channel inputs of a baseband receiver. The selection of which of the I or Q component to place on the I channel input and which other to place on the Q channel input is based on, there being a correct relationship of the I and Q components received from a RF processing stage of a wireless communication device or if the I and Q components have incorrect relationship because they are interchanged.

Abstract: UWB (Ultra Wide Band) interference mitigation. A novel solution is presented whereby various piconet operable devices are operated to support a relatively structured interference pattern. The devices operate cooperatively (e.g., within multiple piconets that may be in relatively close proximity) such that undesirable symbol collisions generate relatively structured interference (e.g., a structured interference pattern). A piconet operable device (e.g., a communication transceiver or receiver) operating therein includes intelligence such that it may detect a symbol that has undergone an undesirable symbol collision. Then, after those symbols have been identified, they may be modified appropriately so the overall performance of the piconet may be kept at a high performance level. For example, those symbols having an energy (or power) above a predetermined threshold (such as an expected energy level or a power level) may be appropriately de-weighted.

Abstract: A physical layer device (PLD) includes a first serializer-deserializer (SERDES) device and a second SERDES device. Each SERDES device includes an analog portion with a serial port that is configured to communicate serial data with various network devices, and a digital portion that is configured to communicate parallel data with other various network devices. The PLD includes a first signal path that is configured to route serial data signals between the analog portions of the SERDES devices, bypassing the digital portions of the SERDES devices. Therefore, the SERDES devices can directly communicate serial data without performing parallel data conversion. A second signal path is configured to route recovered clock and data signals between the analog portions of the SERDES devices, but still bypassing the digital portions of the SERDES devices. The recovered clock and data signals are then regenerated before being transmitted over a network device.

Abstract: A method and system for sorting a number of items in a computer system. The sort is based on a plurality of values of a key. Each item has a value of the plurality of values. The method and system include providing plurality of stages, providing at least one switch coupled between the plurality of stages, and providing a final switch coupled with a last stage. Each of the plurality of stages has a pair of first-in-first-out buffers (FIFOs) that store twice as many of the items as the pair of FIFOs in a previous stage. Each switch is for merging and sorting a first portion of the number of items from the pair of FIFOs in the previous stage based on the key and for providing the first portion of the number plurality of items to a first FIFO of the pair of FIFOs of the stage in order.

Abstract: A dual link receiver terminates, recovers, channel aligns, and link aligns a plurality of primary link channels and a plurality of secondary link channels. The plurality of primary link channels and the plurality of secondary link channels are each received, bit recovered, synchronized, decoded, and channel aligned. Then, the plurality of primary link channels and secondary link channels are link aligned. Link alignment operations first determine a relative misalignment between the plurality of primary link channels and the plurality of secondary link channels. A primary link delay is then applied to the primary link channels and a secondary link delay is then applied to the secondary link channels. A difference between the primary link delay and the secondary link delay is based upon the misalignment between the plurality of primary link channels and the plurality of secondary link channels. An enabling circuit precludes an incorrect blanking period indication.

Abstract: A system and method for enabling communication between power source equipment and a powered device chip. In one embodiment, communication between the power source equipment and the powered device chip is enabled through a communication link established between the powered device chip and a host device on the powered device.

Abstract: An embodiment of the present invention provides a system for implementing a Reed-Solomon computation of parity bytes of a codeword, including an accumulator and a logic circuit. The accumulator is configured to hold a plurality of bits. In an embodiment, each bit held in the accumulator initially corresponds to a bit associated with a data byte of the codeword. In another embodiment, each bit held in the accumulator initially correspond to a fixed value. The logic circuit is configured to iteratively compute a new bit for each bit held in the accumulator. After a last iteration of the computation, the bits held in the accumulator correspond to the parity bytes, wherein for each bit held in the accumulator each iteration of the computation comprises computing an exclusive-OR of a fixed subset of bits held in the accumulator. In an embodiment, the exclusive-OR is computed for the fixed subset of bits held in the accumulator and an input bit of the codeword.

Abstract: A system and method for flexibly outputting audio from a plurality of programs to the particular outputs that are desired for each audio stream. This routing flexibility enables the audio system to operate in a variety of configured usage modes, wherein each usage mode identifies the routing of each audio stream to one or more outputs such as SPDIF, HDMI, I2S, and DAC.

Abstract: A system and method for controlling rate adjustment of audio data to prevent underflow or overflow. In a dual audio/video system, a device can receive two input transport streams. To prevent underflow or overflow of audio data when audio data from a first transport stream is displayed in accordance with a sample rate derived from a second transport stream, a control for rate adjustment is used to match the source sample rate with the display rate. This rate adjustment module can be designed to add or drop audio samples based on a time base comparison or on a STC, PTC, and display rate comparison.