Abstract: A sequence mapping circuit and method for digital audio circuits generates a pulsed output. Over time, the mapping circuit generates pulses with a substantially identical average centroid for each of the possible output waveforms. For at least some of the output waveforms, two or more sets of pulses are provided representing the same waveform but having different centroids. The output is alternated among the available sets of pulses to maintain the desired average centroid over time. Shuffling of the output among the available pulses representing a given waveform may be randomly determined, or the pulses used may be tracked and the output pulses sequentially alternated among the available output pulses. The shuffled mapping method reduces output harmonics compared to conventional static mappers.

Abstract: Close two constituent trellis of a turbo encoder within the interleave block. The state of a multi-state encoder is forced to a known/predetermined state at the end and beginning of each data frame. Packet based and/or frame based data transmissions benefit greatly when the encoder state of a multi-state encoder is known at the beginning and end of each frame. Appropriately chosen symbols, selected to force the encoder to a known state at the end of a data frame, may be padded to the end of a data frame that is to be encoded; this will force the encoder to “close” at the end of the data frame. These closure symbols may also be padded to the end of the data frame before the data frame in interleaved. Moreover, within encoder embodiments that include multiple constituent encoders, both constituent encoders will be forced to the known/predetermined state.

Abstract: A phase based system and method for determining signal consistency (e.g., in a video signal processing system). Various aspects of the present invention may, for example, include receiving a first and second signal, each of which includes a respective first sub-signal. A receiving module may, for example, affect such receiving. The first and second signals may be synchronized according to, at least in part, aspects of their respective first sub-signals. A signal synchronization module may, for example, effect such synchronization. Phase difference between respective sub-signals of the first and second synchronized signals may be determined (e.g., using sample-wise multiplication). Multiplication and accumulator modules may, for example, effect such a determination. A signal may be generated that is indicative of signal consistency based, at least in part, on the determination of phase difference between the respective sub-signals. An output module may, for example, effect such a signal generation.

Abstract: A computer system is disclosed capable of conditionally carrying out an operation defined in a computer instruction. The computer instruction is implemented on so-called packed operands, that is operands containing a plurality of packed objects in respective lanes. An operation defined in the computer instruction is conditionally carried out in dependence on stored condition values which determine for each lane whether or not the operation is to be executed on objects in that lane. An execution unit for a computer system, a computer system and a method of executing instructions are defined.

Abstract: A TDR (Time Domain Reflectometry) circuit associated with a computer network device monitors a network connection to identify changes in that connection. The disclosed system and method may provide notification when a possible attempt to intercept signals in the network has been detected, and may be automatically controlled to perform periodic monitoring of the network.

Abstract: The present invention provides systems and methods for asymmetrically varying gain in a low noise amplifier. The amplifier includes a first stage amplifier, a plurality of second stage amplifiers coupled to the first stage amplifier, a comparator coupled to one of the second stage amplifiers, and a controller coupled to the comparator, the first stage amplifier, and the plurality of second stage amplifiers. The controller is configured to produce one or more gain control signals to change the gain of one of the first stage amplifier or the plurality of second stage amplifiers at a plurality of asymmetric rates so as to cause the power of the output signal to move toward one of the threshold values of the comparator. The rate of change of the gain is based on conditions including the gain of the first stage amplifier, gain of a second stage amplifier, and the sampled power level.

Abstract: An apparatus and method for switching VOIP packets in a data network, wherein the method includes the steps of receiving a first packet in a network switch and determining if the first packet is a VOIP packet. Further, method includes determining a dynamically negotiated VOIP port for a VOIP session from at least one of the first packet and a second packet received in the network switch, if the first packet is determined to be the VOIP packet. Finally, the method includes the steps of classifying all subsequent VOIP packets corresponding to the dynamically negotiated VOIP port in accordance with predetermined parameters. The apparatus includes a network switch having at least one data port interface controller supporting a plurality of data ports for transmitting and receiving data, and a fast filtering processor in communication with the at least one data port interface.

Abstract: A method and system for detecting a dual tone in a composite signal having first and second components including means for separating the composite signal into its first and second components, means for estimating power of the separated first and second components, means for determining frequency of the separated first and second components, and means for comparing the power and frequency of the first and second components to at least one of a plurality of respective power and frequency thresholds to determine whether the composite signal comprises a dual tone.

Abstract: A low-speed DLL facilitates a deskewed interface between a high-speed RX data demultiplexer circuit directly to an Application Specific Integrated Circuit (ASIC) with which it is integrated by locking a 156 MHz ASIC clock to a 156 MHz reference derived from a high speed 2.5 GHz clock. The DLL employs a digital interpolator to generate 32 phases of the 156 MHz clock. The digital interpolator supplies the phases using a double clocked shift register with recirculating feedback. The shift register is double clocked using the 2.5 GHz clock. The register outputs are tapped and fed to a 32:1 multiplexer having a phase select input that is controlled by the phase difference signal generated by the DLL. The phase difference control signal is converted to a digital representation of its magnitude by which the requisite number of phase shift increments may be selected.

Abstract: A system and technique for detecting a device that requires power is implemented with a power detection station. The power detection system includes a detector having an output and a return which are coupled together by the device when the device requires power. The detector includes a word generator for generating test pulses for transmission to the device via the detector output, and a comparator for comparing the detector output with the detector return. The power detection station has a wide variety of applications, including by way of example, a switch or hub.

Abstract: A linearized oscillation synthesizer includes a phase and frequency detection module, charge pump circuit, low pass filter, voltage control oscillator, and a feedback module. The phase and frequency detection module is operably coupled to produce a charge-up signal, a charge-down signal, and an off signal based on phase and/or frequency differences between a reference oscillation and a feedback oscillation. The reference oscillation is generated by a clock source such as a crystal oscillator while the divider module generates the feedback oscillation by dividing the output oscillation by a divider value. The charge pump circuit produces a positive current in response to the charge-up signal, a negative current in response to the charge-down signal and also produces a non-zero offset current. The non-zero offset current shifts the steady state operating condition, and other operating conditions, of the charge pump into a linear region of charge pump performance curve.

Abstract: Modular, portable data collection terminals are disclosed for use in mixed wireless and hard-wired RF communication networks, wherein various radio transmitter modules and associated antennas may be selectively added to a base terminal unit to solve networking problems associated with specific types of business environments. Modularity exists in both the hardware (splitting data collection and processing control circuitry from radio transceiver control circuitry) and software (splitting transceiver-specific, lower level communication protocol from generic, higher level communication protocol). The control circuitry, including associated microprocessors devices, interact to selectively activate communication circuits to perform necessary communication or data processing functions and enter and remain in a power-saving dormant state during other times. To support such dormant or “sleeping” states, a series of communication protocols provide for channel access to the communication network.

Abstract: Often programmable gain attenuators (PGAs) are combined with high pass filters. Adjustment of the highpass filter however can have unintended effects, such as changing the step size of the PGA. By placing the resistance of the highpass filter in parallel with a programmable attenuator divider, the steps of the PGA can be minimally affected as the highpass frequency is adjusted.

Abstract: A hierarchical memory structure having memory cells, and sense amplifiers and decoders coupled with the memory cells to form first tier memory module, and subsequent tiers being formed by having (n?1)-tier memory modules, which are coupled with (n)-tier sense amplifiers and (n)-tier decoders. Also provided are a single-ended sense amplifier having sample-and-hold reference, and a charge-share limited-swing-driver sense amplifier; an asynchronously-resettable decoder; a wordline decoder having row redundancy; a redundancy device having redundant memory cells operated by a redundancy controller; a diffusion replica delay circuit; a high-precision delay measurement circuit; and a data transfer bus circuit imposing a limited voltage swing on a data bus. Methods are provided for a write-after-read operation without an interposed precharge cycle, and write-after-write operation with an interposed precharge cycle are provided, either operation being completed in less than one memory access cycle.

Abstract: In wireless communications such as in the Bluetooth communication system, an execution unit sequentially receives software instructions for execution. Prior to completing each instruction, the execution unit issues an interrupt indicating the upcoming completion of the instruction execution and awaits receipt of the next instruction. A Link Manager issues limited instructions, and a Link Controller includes a hardware execution unit for executing the limited instructions. A processing unit in the Link Manager performs remaining functions under control of a software program.

Abstract: Methods and apparatus are provided for performing authentication and decryption operations. A record including multiple encrypted blocks is received. An encrypted block in the record is extracted and decrypted first in order to obtain context information for performing authentication operations. Each remaining block is then decrypted and authenticated by using the available context information. Authentication operations can be performed without having to wait for the decryption of all of the blocks in the record.

Abstract: An exemplary embodiment of the present invention described and shown in the specification and drawings is a transceiver with a receiver, a transmitter, a local oscillator (LO) generator, a controller, and a self-testing unit. All of these components can be packaged for integration into a single IC including components such as filters and inductors. The controller for adaptive programming and calibration of the receiver, transmitter and LO generator. The self-testing unit generates is used to determine the gain, frequency characteristics, selectivity, noise floor, and distortion behavior of the receiver, transmitter and LO generator. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or the meaning of the claims.

Abstract: A phase locked loop that includes such a loop filter, the phase locked loop includes a difference detector, programmable charge pump, fixed loop filter, voltage controlled oscillator and adjustable divider module. The difference detector is operably coupled to determine a different signal based on differences in phase and/or frequency between a reference oscillation and a feedback oscillation. The programmable charge pump is operably coupled to generate a charge current based on the difference signal and a scaling signal. The fixed loop filter is operably coupled to convert the charge current into a control voltage. The voltage controlled oscillator generates an output oscillation based on the control voltage and the adjustable divider module generates the feedback oscillation based on the output oscillation and a divider value. The scaling module is operably coupled to produce the scaling signal based on the selected divider.

Abstract: A method, system, and a computer program product for filtering palettized image formats are presented. In an embodiment, data is retrieved from a palette of an image. Data associated with a channel of the palette is filtered, and stored, for example, together with a pixel buffer of the image to form a filtered image. Additionally, a method, system, and a computer program product for displaying images stored in a modified palettized image format are presented. In an embodiment, data is retrieved from a palette and from a pixel buffer of an image stored in modified palettized image format. Filtered pixels of the image are formed by combining, for each pixel in the pixel buffer, data retrieved from the palette with filtered data, retrieved from the pixel buffer. The modified palettized image is rendered on a display by displaying the filtered pixels.

Abstract: Systems and methods for pulse stretching architectures for phase alignment of multi-frequency clocks for high speed data acquisitions are disclosed. A high speed data acquisition system includes a transmitter and a receiver. The receiver includes a multi-frequency clock generator that generates a plurality of clock signals, a pattern check module that detects a test pattern received from the transmitter and outputs a stretch command signal, and a stretch pulse generator that receives the stretch command signal and provides a stretch pulse signal that aligns the phases of the plurality of clock signals generated by the multi-frequency clock generator. Methods for initializing and shifting multi-phase clock signals to optimize error performance of a high speed data acquisition system are also provided.