Abstract: A radio transceiver includes amplification circuitry that is coupled to receive a down converted signal and to provide infinite rejection of any DC component added by the down conversion circuitry. Specifically, an amplification stage includes a voltage integrator that is coupled within a feedback loop of the amplification circuitry to produce a DC charge having a magnitude that equals the added DC component but a polarity that is opposite. Accordingly, the voltage produced by the voltage integrator is added to the signal received from the down conversion circuitry to cause the amplification circuitry to merely amplify the wireless communication signals characterized by a frequency of oscillation. Logic circuitry is used for selectively coupling the voltage integrator to an output port of the amplification circuitry.

Abstract: A system includes a bus and a circuit for precharging the bus. The circuit may be coupled to receive a clock signal associated with the bus, and may be configured to precharge a bus during an interval of the period of the clock signal, the interval being between a first edge (rising or falling) and the subsequent edge (falling or rising). A second interval within the period and excluding the interval may be used to perform a bus transfer. In this manner, both precharging and transfer may be performed in the same clock cycle. Bandwidth of the bus may be improved since transfers may occur each clock cycle, rather than having a non-transfer clock cycle for precharging.

Abstract: A technique is described for reliably determining whether a direct digital connection exists between a transmitting server modem and a receiving client modem. Such a determination is an essential part of the training procedure for modems that conform to ITU-T Recommendation V.90 but is also applicable to other data communications configurations and equipment. In some configurations in accordance with the present invention, segments of a modem training signal, L1L2, are used to make the determination.

Abstract: A data switch for network communications includes a first data port interface which supports at least one data port which transmits and receives data. A second data port interface is also provided supporting at least one data port transmitting and receiving data. A CPU interface is provided, with the CPU interface configured to communicate with a CPU. A common memory is provided, and communicates with the first data port interface and the second data port interface. A memory management unit is provided, and communicates data from the first data port interface and the second data port interface and an common memory. At least two sets of communication channels are provided, with each of the communication channels communicating data and messaging information between the first data port interface, the second data port interface, and the memory management unit.

Abstract: A system may include two or more agents, one of which may be identified as a default agent. If none of the agents arbitrate for the bus, the default agent may be given a default grant of the bus. If the default agent has information to transfer on the bus, the default agent may take the default grant and my transfer the information without first arbitrating for the bus and winning the arbitration. In one embodiment, the default agent may arbitrate for the bus when it has information to transfer and no default grant is received. The default agent may be an equal participant in arbitration. A fair arbitration scheme may thus be implemented in arbitrations in which there is contention for the bus.

Abstract: Reliable detection of a call-waiting tone is provided by employing a correlation based technique. A modem or other device employing such a technique need not rely on carrier drop detection and is generally insensitive to other energy or noise on the line.

Abstract: A Multi-tone transmission system processes input data through a plurality of intermediate processing stages 12, 14, 16 and corresponding stages of intermediate data 18, 20. A symbol including a number of tones is obtained therefrom by an inverse Fourier transform 24 and stored in a buffer 158. The peak amplitude contained in the symbol is detected 28 and compared with a threshold. If the peak amplitude in the symbol exceeds the threshold, the symbol stored in the buffer 158 is regenerated.

Abstract: An integrated communications system. Comprising a substrate having a receiver disposed on the substrate for converting a received signal to an IF signal. Coupled to a VGA for low voltage applications and coupled to the receiver for processing the IF signal. The VGA includes a bank pair having a first bank of differential pairs of transistors and a second bank of differential pairs of transistors. The bank pair is cross-coupled in parallel, the IF signal is applied to the bank pair decoupled from a control signal used to control transconductance output gain of the bank pair over a range of input voltages. A digital IF demodulator is disposed on the substrate and coupled to the VGA for low voltage applications, for converting the IF signal to a demodulated baseband signal. And a transmitter is disposed on the substrate operating in cooperation with the receiver to establish a two way communications path.

Abstract: The present invention is directed to a telephone equipped with multiple microphones that provides improved performance during operation of the telephone in a speaker-phone mode. For example, the multiple microphones can be used to improve voice activity detection, which in turn, can improve echo cancellation. In addition, the multiple microphones can be configured as an adaptive microphone array and used to reduce the effects of (i) room reverberation, when a near-end user is speaking, and/or (ii) acoustic echo, when a far-end user is speaking.

Abstract: An adaptive, reduced-complexity soft-output maximum-likelihood detector that is operable to process data by adaptively selecting a processing scheme based on a determination of signal quality. The signal quality is derived as a function of the noise, the modulation format, the channel (the communication environment), the transmit signal power and the receive signal power. If the signal quality is low, the signal is processed using a maximum likelihood detector. If, however, the signal quality is high, a simpler sub-optimal detector is used. By estimating the signal quality and choosing an appropriate detection method, the present invention ensures accurate detection of incoming data signals in a MIMO communication system while maintaining the highest possible processing speed.

Abstract: A computer system for conditionally performing an operation defined in a computer instruction, an execution unit of the computer system comprises at least one operand store for holding operands on which an operation defined in an instruction is to be performed, wherein said operand store defines a plurality of lanes each holding an object, a plurality of operators associated respectively with the lanes for carrying out an operation specified in an instruction on objects in the operand lanes, a destination store for holding objects resulting from the operation on a lane by lane basis, a plurality of control stores each comprising a plurality of indicators to control for each lane whether or not an operation defined in an instruction is to be performed on that lane, and control circuitry for controlling which of said plurality of control stores is to be used to control per lane execution of an instruction, the control circuitry being operative to select a control store from the plurality of control stores based

Abstract: A reduced-complexity maximum-likelihood detector that provides a high degree of signal detection accuracy while maintaining high processing speeds. A communication system implementing the present invention comprises a plurality of transmit sources operable to transmit a plurality of symbols over a plurality of channels, wherein the detector is operable to receive symbols corresponding to the transmitted symbols. The detector processes the received symbols to obtain initial estimates of the transmitted symbols and then uses the initial estimates to generate a plurality of reduced search sets. The reduced search sets are then used to generate decisions for detecting the transmitted symbols. In various embodiments of the invention, the decisions for detecting the symbols can be hard decisions or soft decisions.

Abstract: A metal-insulator-metal (MIM) capacitor is made according to a copper dual-damascene process. A first copper or copper alloy metal layer if formed on a substrate. A portion of the first metal layer is utilized as the lower plate of the MIM capacitor. An etch stop dielectric layer is used during etching of subsequent layers. A portion of an etch stop layer is not removed and is utilized as the insulator for the MIM capacitor. A second copper or copper alloy metal layer is later formed on the substrate. A portion of the second metal layer is utilized as the upper plate of the MIM capacitor.

Abstract: A gain boost circuit and methodology are described for providing improved gain boosting with tuned amplifier circuits, such as differential low noise amplifier circuits having output resonant tank circuits. By selectively controlling the current source for a negative transconductance stage coupled between the differential amplifier output and the output resonant tank circuits, the amplifier gain may be adjusted to compensate for temperature variations. In addition, the amplifier gain boost may be selectively added, removed or even incrementally adjusted by using a current source control circuit in the negative transconductance stage to adjust the negative transconductance value generated by the negative transconductance stage.

Abstract: A Radio Frequency (RF) circuit includes an active portion and a tuned portion. The active portion receives an RF signal and that operates upon the RF signal. The tuned portion couples to the active portion and includes a first inductor, a second inductor, and an NMOS transistor. The NMOS transistor has a gate, a drain, a source, and a body. The drain and source operably couple/decouple the second inductor to/from the first inductor. The drain and source are biased at respective operating voltages (greater than ground and less than a first voltage supply) by the active portion and the tuning portion. The body couples to a first voltage supply, via a control circuit or switch in some cases. Applying a second voltage supply (that is greater than the first voltage supply) to the gate turns ON the NMOS transistor.

Abstract: A method and apparatus for dynamically managing power in a wireless interface device while maintaining an acceptable bit error rate. The wireless interface device includes a wireless interface unit, a bit error detection unit that monitors the bit error rate a data stream in the wireless interface unit, a processing unit, and a power management unit. The power management unit operates in a conjunction with the processing unit and the bit error detection unit to monitor the bit error rate and to dynamically adjust the voltage levels in the wireless interface unit to ensure that the bit error rate remains in an acceptable range.

Abstract: A power amplifier power amplifier includes a transconductance stage and a cascode stage. The transconductance stage that is operable to receive an input voltage signal and to produce an output current signal. The transconductance stage includes a first Metal Oxide Silicon (MOS) transistor having a first gate oxide thickness and a first channel length. The cascode stage communicatively couples to the transconductance stage and is operable to receive the output current signal and to produce an output voltage signal based thereupon. The cascode stage includes a second MOS transistor having a second gate oxide thickness and a second channel length.

Abstract: Provided are a method and system for reducing glitch in a switch circuit. A system includes a current-steering switch circuit including a main differential pair switch coupled to a first tail current having a first current value. Also included is an auxiliary differential pair switch connected to the main differential pair switch. The auxiliary differential pair switch is coupled to a second tail current and configured to substantially reduce a feed-through current associated with the main differential pair switch.

Abstract: A method of presenting a selected portion of graphical images within a wireless terminal that includes receiving an original graphical image, having a source resolution, to be presented on a display screen. The native pixel resolution of the display screen may differ from that of the original graphical image. A complex decimation pattern when applied to the selected portion of the image allows the selected portion of the original graphical image to be resized from the source resolution to a decimated resolution operable to be displayed within the native resolution of the display screen. Decimated pixels need not be further processed to reduce the processing requirements imposed on the system processor. Operations normally associated with the decimated portions of the image may be offloaded from the processing module to improve system efficiency.

Abstract: A system and method for noise cancellation in a signal-processing circuit (e.g., an analog-to-digital converter circuit). Various aspects of the present invention may comprise inputting a first input signal and a digital input signal to the signal-processing circuit. The digital input signal may, for example, comprise a digital dither signal or other processor control signal. The signal-processing circuit may, for example, output a signal comprising a first signal component that is primarily a function of the first input signal and a second signal component that is primarily a function of the digital input signal. The second signal component may be estimated based on estimated behavior of the signal-processing circuit in response to the digital input signal. The estimated second signal component may, for example, be substantially removed from the signal-processing circuit output signal.