Abstract: A power amplifier power amplifier includes a transconductance stage and a cascode stage. The transconductance stage that is operable to receive an input voltage signal and to produce an output current signal. The transconductance stage includes a first Metal Oxide Silicon (MOS) transistor having a first gate oxide thickness and a first channel length. The cascode stage communicatively couples to the transconductance stage and is operable to receive the output current signal and to produce an output voltage signal based thereupon. The cascode stage includes a second MOS transistor having a second gate oxide thickness and a second channel length.

Abstract: A circuit is provided for reducing mismatches between the outputs of successive pairs of cells in an analog to digital converter. A voltage input means is coupled to a first input terminal of each cell to introduce and an input voltage. A reference voltage means is coupled to a second input terminal of each cell to introduce progressive fractions of a reference voltage. A low impedance means is coupled between corresponding first output terminals and coupled between corresponding second output terminals in successive cells, to draw load-bearing currents to the successive cells, affecting the relative voltages and thereby reducing the effects of cell mismatches on these output terminals. Lastly, a high impedance means is coupled to the each of the first output terminals and to each of the second output terminals in successive cells.

Abstract: A method and system, compatible with low-voltage CMOS technology, for controlling the charging of a battery. The method includes monitoring a battery voltage with respect to a threshold voltage. The method further includes coupling a charging control logic supply to ground, generating an active low first control signal, inverting the active low first control signal, and charging the battery at a first rate when the battery voltage is below the threshold voltage. The method further includes coupling the charging control logic supply to the battery voltage, generating an active high second control signal, and charging the battery at a second rate when the battery voltage exceeds the threshold voltage. The first charging rate is slower than the second charging rate. The method further includes supplying battery power to a charger line when the battery voltage exceeds the charger voltage, and suppressing a leakage current.

Abstract: A system and method for noise cancellation in a signal-processing circuit (e.g., an analog-to-digital converter circuit). Various aspects of the present invention may comprise inputting a first input signal and a digital input signal to the signal-processing circuit. The digital input signal may, for example, comprise a digital dither signal or other processor control signal. The signal-processing circuit may, for example, output a signal comprising a first signal component that is primarily a function of the first input signal and a second signal component that is primarily a function of the digital input signal. The second signal component may be estimated based on estimated behavior of the signal-processing circuit in response to the digital input signal. The estimated second signal component may, for example, be substantially removed from the signal-processing circuit output signal.

Abstract: To adjust transmit power of a DSL modem, an estimated electrical length of a loop is first determined when a 1st DSL modem at a 1st location transmits a plurality of signals to a 2nd DSL modem at a 2nd location. Each of the signals transmitted by the 1st DSL modem have a known frequency and are transmitted at a known power level. Upon receiving the signals, the 2nd DSL modem determines the received power level for each of the signals. The 2nd DSL modem then estimates an electrical length of a loop between the 1st and 2nd DSL modems for each of the signals received. The 2nd DSL modem then processes a plurality of estimated electrical lengths in accordance with a function to produce a determined electrical length. Having determined the electrical length, the 2nd DSL modem adjusts its transmit power accordingly.

Abstract: The present invention is directed to a system and method of sending packets between ports on trunked network switches. A trunk connection is provided between first and second switches, with the trunk connection including at least two of the plurality of ports from the first switch being connected to at least two of the plurality of ports of the second switch. A packet is received at an ingress submodule of the first switch, and a lookup is performed on one of a source address and a destination address of the packet based upon a lookup table provided in the ingress submodule. A rules tag bit is then compared to a rules table defining which trunk port of the trunk bundle will be used for communication. The rules tag determines which address bits will be used to identify a trunk port for communication.

Abstract: A display engine of a video and graphics system includes one or more processing elements and receives graphics from a memory. The graphics data define multiple graphics layers, and the processing elements process two or more graphics layers in parallel to generate blended graphics. Alpha values may be used while blending graphics. The processing elements may be integrated on an integrated circuit chip with an input for receiving the graphics data and other video and graphics components. The display engine may also include a graphics controller for receiving two or more graphics layers in parallel, for arranging the graphics layers in an order suitable for parallel processing, and for providing the arranged graphics layers to the processing elements. The blended graphics may be blended with HDTV video or SDTV video, which may be extracted from compressed data streams such as an MPEG Transport stream.

Abstract: A method and apparatus for searching an electronically stored table of information including a plurality of table entries and facilitating high speed searching of a table to provide a longest matching entry. The table searching method uses at least one memory unit having a table of information including a plurality of data entries. The table of information has a plurality of search keys associated with the plurality of data entries and the plurality of search keys form a tree structure based on a prefix length for each of the search keys. The plurality of search keys are expanded such that each of the plurality of search keys has two lowest level search keys associated therewith that cover a lowest level of the tree structure. A binary search of the lowest level search keys is performed based on a search value to determine a longest prefix match. A data entry of the plurality of data entries is output based on said longest prefix match.

Abstract: Methods and systems for increasing an amplifier circuit's Q factor are disclosed herein. The method may comprise coupling a first LC tank to a source of a single switching transistor and coupling a second LC tank to a drain of the single switching transistor. A gate of the single switching transistor may be controlled by an amplifier core coupled to the first LC tank and the second LC tank. A resistance of the first LC tank and the second LC tank may be decreased by about one half, which increases the Q factor by about two. The gate of the single switching transistor may be controlled by a control signal generator coupled to the amplifier core. The first LC tank and/or the second LC tank may be tuned to a frequency of about 3.4 GHz to 4 GHz. The single switching transistor may comprise an NMOS transistor.

Abstract: A system and method is provided for interleaving data in a communications device. The system includes a memory for storing symbols of a data block, a read module and a write module, each of which is coupled to the memory. The system also includes a interleaving logic module coupled to the read and write modules. The interleaving logic module determines an interleaving sequence comprising a sequence of memory addresses. Each memory address is then communicated sequentially to the read and write modules. When the read module receives the address, the read module reads the stored data symbol. When the write module receives the address, the write module writes a symbol from a next data block to the vacated address. The interleaving logic module repeats these steps until every symbol of the stored block has been read and every symbol of the next data block has been written to memory.

Abstract: A printed bandpass filter is mounted on a precision substrate to eliminate the need for post-fabrication tuning. The filter input is capacitively coupled to a series of quarter wavelength resonators and the filter output. The quarter wavelength resonators are printed as spirals to reduce filter size. The resonators define the bandpass characteristics of the filter. The filter also weakly couples the input signal to the filter output in a manner to cancel the signal image. Mechanical clips mitigate thermal stress on solder connections when the precision substrate is mounted on a second printed circuit board.

Abstract: A differential amplifier is configured in a cascode configuration that includes input transistors that are connected to corresponding cascode transistors. The gates of the cascode transistors are tied together to form a common bias for the cascode devices. The input transistors of the differential amplifier receive a differential input signal that is amplified and outputted to an output circuit that is connected to the cascode transistors. The cascode devices require a bias voltage for proper operation. Preferably, the bias voltage puts the cascode devices into the saturation region. The gates of cascode devices are coupled together and connected to a bias terminal. In embodiments of the invention, the bias terminal is connected to another terminal of the chip to provide the bias for the cascode devices. This can include the input and output nodes if they have a well-defined and relatively fixed voltage.

Abstract: A multi-port transceiver includes a transmitter and receiver for each port. The invention is a test method and apparatus for testing individual components in the transmit and receive paths. Specifically, the invention includes a method of testing the full range of a programmable gain amplifier (PGA) and an analog to digital converter (ADC) in the receive path of each port. This is accomplished by connecting the transmitter of one port directly to the receiver of a second port, and varying the amplitude of the transmitter over a range of gain settings of the PGA while examining if the dynamic range of the receiver has been exceeded.

Abstract: A method is disclosed for maintaining the integrity of a communication system. The method comprises detecting common path distortion (CPD) and periodic impulse/burst (PIB) noise in a received signal in the communication system. After isolating the CPD and PIB noise, ingress noise in the received signal is identified. Isolating the CPD and PIB noise thus prevents improper classification of CPD and PIB noise as ingress noise. Operating parameters of the communication system are then adapted in accordance with the identified ingress noise, the detected CPD and/or the detected PIB noise.

Abstract: Inter-device adaptable interfacing clock skewing. The invention is operable in either one of both of a transmit mode and a receive mode to perform skewing of a transmitted and/or a received signal. The operational parameters including frequency and phase may be determined during auto detect/auto negotiation, they may be programmed externally, or they may be user selected in various embodiments. A device may include a clock generator, one or more divider, and one or more delay cells internally to the device. If desired, a high frequency clock is generated within the device and then divided down to generate the appropriate clock signal that supports the communication and interaction between multiple devices. Registers and/or pins may be used to select the clock frequency and phase of output clock signals. The present invention supports multiple Ethernet protocols between multiple devices including 10BaseT, 100BaseT, and 1000BaseT.

Abstract: Methods and apparatus for improving the current matching within current mirror circuits in applications such as low voltage integrated circuits. Embodiments of the present invention attempt to maintain the proper current ratio between reference and output supplies by adjusting the reference output of the current mirror. An existing reference voltage on the output side of the mirror can be used or a reference voltage can be created to be used for the voltage regulation of the reference side of the current mirror.

Abstract: A method and system for performing diagnostic tests on a communications system. Diagnostic test signals are generated by a transceiver included within the communications system. Diagnostic data signals generated within the communications system in response to the diagnostic test signals are collected by the transceiver. The communications transceiver may operate alone, with an assisting communications transceiver, or with a non-assisting communications transceiver. The collected diagnostic data signals are stored and made available for later analysis. The method and system are used to generate and store ECHO Crosstalk, Near End Cross Talk (NEXT) and Far End CrossTalk (FEXT) data signals.

Abstract: Auto-negotiation with a communication partner includes downgrading a set of advertised communications capabilities, e.g., IEEE 802.3 capabilities, when a link with the communication partners fails to support an advertised communications capability, e.g., wire-speed.

Abstract: A method to perform DC compensation on a Radio Frequency (RF) burst transmitted between a servicing base station and a wireless terminal in a cellular wireless communication system that first receives the RF burst modulated according to either a first or second modulation format. Samples from the RF burst, or taken from the training sequence, are produced and averaged to produce a DC offset estimate. The DC offset estimate is then subtracted from each of the samples. The modulation format of RF burst may then be identified from the samples. Depending on the identified modulation format, the DC offset estimate may be re-added to the samples when a particular modulation format is identified as the modulation format of the RF burst. This decision is made based on how well various components within the wireless terminal perform DC offset compensation.

Abstract: A Variable Gain Amplifier (VGA) amplifies an input signal according to a gain, to produce an amplified signal. A detector module detects a power indicative of a power of the amplified signal. A comparator module compares the detected power to a high threshold, a low threshold and a target threshold intermediate the high and low thresholds. A controller module changes the gain of the VGA so as to drive the detected power in a direction toward the middle threshold when the comparator module indicates the detected power is not between the high and low thresholds.