Abstract: A super set of orthogonal space-time block codes is combined with set partitioning to form super-orthogonal space-time trellis codes having full diversity, enhanced coding gains, and improved rates. In communications systems, these codes are implemented by an encoder of a diverse transmitter to send an information signal to a receiver having one or more receiver elements. A decoder in the receiver decodes the encoded signal to reproduce the information signal. A method of the invention is used to generate set portioning structures and trellis structures that enable code designers to systematically design the codes of the invention.

Abstract: A system and method use an aligning device to align clock signals of two logic devices before data transfer between them. In this example, the aligning device aligns a clock signal of a sequencer with a clock signal of a storage device before the sequencer transfers data to the storage device. The aligning device includes a phase detector that receives a first reference clock signal, which is used to control the storage device, and a delayed signal, which is used to control the sequencer, and generates a comparison clock signal. The comparison clock signal is filtered before being used to control a phase of a second reference clock signal, which is related to the first reference clock signal. The phase controlled second clock signal is an aligning clock signal that is feed back to a delay device to produce one or more subsequent delay device clock signals that are aligned to the storage device clock or first reference clock signal.

Abstract: A point-to-multipoint network interface is provided that is simpler and less costly to implement than conventional Ethernet switches. The interface includes a plurality of downstream transmitters for transmitting data packets to a plurality of end user devices, a plurality of downstream receivers for receiving data packets from the plurality of end user devices, an upstream transmitter and an upstream receiver. A multiplexer within the interface multiplexes data packets received from the end user devices into a stream of data packets for transmission to a higher level node regardless of the destination address of the data packets. Conversely, a demultiplexer within the interface demultiplexes a stream of data packets received from the higher level node into individual data packets for selective transmission to one of the plurality of end user devices. The interface can support asymmetrical transmission rates on the upstream and downstream channels between the interface and the end user devices.

Abstract: A transceiver circuit having 10 mb and 100 mb transmit and receive circuitries using the power saving methods allows for power consumption of the transceiver circuit to be significantly reduced. This is accomplished by providing each defined subcircuit with its own power supply and means of activation and deactivation. However, the method for activating and deactivating digital subcircuits and analog subcircuits are different and therefore different types of control signals and methods are provided. Furthermore, there are two general types of power-saving situations. The first type is near total circuit power-down and the second type is partial circuit power-down. In yet another embodiment, a method for minimizing energy usage during the idle period is utilized.

Abstract: An FM radio receiver includes a low noise amplifier, down conversion mixing module, local oscillation module, bandpass filter, demodulation module, and a DC offset estimation module. The low noise amplifier, the down conversion mixing module, the bandpass filter, and the demodulation module are operably coupled to recapture data from a received a radio frequency (RF) signal. The local oscillation module is operably coupled to generate the local oscillation based on a reference oscillation and a DC offset correction signal. The DC offset estimation module is operably coupled to generate the DC offset correction signal based on a determined a DC offset. The DC offset estimation module determines the DC offset prior to compensation of the local oscillation, such as during a test sequence and/or during a preamble.

Abstract: A wireless transceiver includes a Radio Frequency (RF) transceiver, a baseband transmitter section, and a baseband receiver section. The baseband receiver section receives a baseband signal from the RF transceiver, extracts data therefrom, and provides the data to a host system. The baseband receiver section includes a programmable gain amplifier, an Analog-to-Digital Converter (ADC), a symbol timing compensation section, an RF carrier compensation section, a decision feedback equalizer section, and a preamble processor. The symbol timing compensation section modifies the samples of the baseband signal to compensate for symbol timing variations between a symbol clock of the wireless device and a symbol clock of a transmitting wireless device. The RF carrier compensation section modifies the samples of the baseband signal to compensate for RF carrier variations between an RF carrier of the wireless device and an RF carrier of the transmitting wireless device.

Abstract: A modifiable circuit for coupling at least two adjacent logic blocks in an integrated circuit chip is disclosed. The chip includes a plurality of metal layers and first and second power supply potentials. The circuit comprises a first and second metal interconnect structures, and an interconnect. The first metal interconnect structure traverses the plurality of metal layers using a first plurality of vias, wherein the first metal interconnect structure is located at a boundary of the at least two adjacent logic blocks. The second metal interconnect structure traverses the plurality of metal layers using a second plurality of vias, wherein the second metal interconnect structure is located at the boundary of the at least two adjacent logic blocks.

Abstract: A system and method are disclosed for performing digital multi-channel decoding of a BTSC composite audio signal. Analog-to-digital conversion is performed on a composite analog audio signal at a fast clock rate to generate a composite digital audio signal at a first sample rate. Digital frequency compensation is performed on the composite digital audio signal at the first sample rate to generate a compensated composite audio signal. Digital channel demodulation and filtering are performed on the compensated composite audio signal at the first sample rate to generate a first single channel audio signal at a second sample rate.

Abstract: An error compensation bias circuit and method for a canonic signed digit (CSD) fixed-width multiplier that receives a W-bit input and produces a W-bit product. Truncated bits of the multiplier are divided into two groups (a major group and a minor group) depending upon their effects on quantization error. An error compensation bias is expressed in terms of the truncated bits in the major group. The effects of the remaining truncated bits in the minor group are taken into account by a probabilistic estimation. The error compensation bias circuit typically requires only a few logic gates to implement.

Abstract: Systems and methods are disclosed for arbitrating requests from a plurality of clients requesting access to a shared real-time resource. In one embodiment, a plurality of sub-clients are aggregated into an aggregate client. At the aggregate client, access requests from the sub-clients are arbitrated to generate an aggregate request. An aggregate deadline is determined and access requests from the aggregate client and other clients are arbitrated using the aggregate deadline as the deadline of the aggregate client. In one embodiment, a critical instant analysis of the system is performed using the aggregate deadline as the deadline of the aggregate client. In another embodiment, a block-out counter is employed at an aggregate client to regulate the rate at which the aggregate client provides access requests to the shared resource.

Abstract: An on chip diversity antenna switch includes a first switch, a second switch, a third switch, and a fourth switch. The first switch is operably coupled to a pin associated with a first antenna, to a transmit path and to receive a transmit receive (T/R) control signal. The second switch is operably coupled to the pin associated with the first antenna, to a receive path, and to receive the T/R control signal. The third switch is operably coupled to a pin associated with a second antenna, the transmit path, and to receive the T/R control signal. The fourth switch is operably coupled to the pin associated with the second antenna, to the receive path, and to receive the T/R control signal. Based on the T/R control signal, the first or second antenna is coupled to the transmit or receive path via a single switch.

Abstract: Methods and systems for on-chip processing of data are disclosed. Aspects of the method may include generating a plurality of data processing commands for data compression. A first string of characters may be encoded in one operating cycle utilizing the generated plurality of data processing commands for data compression. The plurality of data processing commands may comprise a branch command, a register moving command, a register setting command, a memory load command, a memory store command, and/or a register compare command. The generated plurality of data processing commands may be stored. At least a portion of the stored data processing commands may be decoded. The decoded portion of the stored data processing commands may be sequenced. The first string of characters may be acquired from a character space. The acquired first string of characters may be matched with at least one existing codeword.

Abstract: A programmable multi-stage amplifier includes a 1st programmable amplifier, a 2nd programmable amplifier, and a control module. The 1st and 2nd programmable amplifiers are coupled in series to amplify an input signal. Each of the 1st and 2nd programmable amplifiers is operably coupled to receive independent gain control signals from the control module. The control module generates the gain control signals by determining the overall gain desired for the programmable multi-stage amplifier and a corresponding gain for each of the 1st and 2nd programmable amplifiers. The factors in which the control module makes this determination are based on an optimization of at least one of the power level of the programmable multi-stage amplifier, the noise factor for the programmable multi-stage amplifier, and/or linearity of the programmable multi-stage amplifier.

Abstract: A technique for determining a symbol erasure threshold for a received communication signal containing symbol information is disclosed. The technique begins by performing a first threshold calculation to produce an initial symbol erasure threshold, then performing a first margin calculation to produce an initial symbol erasure margin and then modifying the initial symbol erasure threshold using the initial symbol erasure margin to produce a modified symbol erasure threshold. By then periodically modifying the modified symbol erasure threshold adaptive via updating the symbol erasure threshold and/or symbol erasure margin based on various error quantities, the technique can compensate for time-variant considerations, such as drifting noise levels.

Abstract: A system and method of assembling a ball grid array (BGA) package with IC die support is described. A stiffener is attached to a substrate that includes a centrally located opening with an integrated circuit (IC) die support structure removably held therein. An IC die is mounted to a central region of the stiffener. Further assembly process steps may be performed on the BGA package with IC die support. The IC die support structure is removed from the centrally located opening. In aspects of the invention, the IC die support structure is removably held in the opening by an adhesive tape or by one or more substrate tabs.

Abstract: A differential line driver includes a plurality of driver cells. Control logic outputs positive and negative control signals to the driver cells so as to match a combined output impedance of the driver cells at (Vop, Von). Each driver cell includes an input Vip and an input Vin, an output Vop and an output Von, a first PMOS transistor and a first NMOS transistor having gates driven by the input Vip, and a second PMOS transistor and a second NMOS transistor having gates driven by the input Vin. A source of the first PMOS transistor is connected to a source of the second PMOS transistor. A source of the first NMOS transistor is connected to a source of the second NMOS transistor. First and second resistors are connected in series between the first PMOS transistor and the first NMOS transistor, and connected together at Von. Third and fourth resistors are connected in series between the second PMOS transistor and the second NMOS transistor, and connected together at Vop.

Abstract: A data processor comprising: a register memory comprising an array of memory cells extending in two dimensions, the cells being located on rows in the first dimension and columns in the second dimension, each cell being addressable by means of an instruction specifying a pair of coordinates that identify the row and column of the cell in the array; and a processing unit capable of executing instructions that operate on a plurality of memory cells in the register, the instructions identifying the plurality of cells by means of a first instruction part specifying a pair of coordinates that identify a first cell in the array, and a second instruction part that identifies the configuration of the plurality of cells relative to the first cell; the data processor being arranged to interpret a first form of second instruction part as specifying a first group of cells all of which are located in the same row but in different columns, and to interpret a second form of second instruction part as specifying a first grou

Abstract: A digital-to-analog converter (DAC) disposed in a data transmission path to convert data from a digital format to an analog format to be transmitted is powered down during a receive mode of operation for a wireless communication device. Likewise, an analog-to-digital converter (ADC) disposed in a data reception path to convert received data from an analog format to a digital format is powered down during a transmit mode of operation.

Abstract: A method for decoding an algebraic-coded message including determining a discrepancy indicator; determining an error locator polynomial according to a modified Berlekamp-Massey algorithm such that an uncorrectable message is detected; and producing a perceptible indication of the detected uncorrectable message. An apparatus includes storage devices, arithmetic components, and an uncorrectable message detector.

Abstract: A method, system and computer program product to adjust transfer rates on conductors in a multi-conductor cable comprising monitoring signals received on each conductor, determining a Signal to Noise Ratio (SNR) for each conductor and adjusting a transfer rate on one or more conductors based on the corresponding SNR. In an embodiment the multi-conductor cable is a twisted pair Ethernet cable. The method further comprises determining whether a conductor is transmitting at an optimal transfer rate as a function of its SNR, calculating an optimal transfer rate for each conductor as a function of its SNR and periodically measuring a change in SNR on each conductor. If the change in SNR is greater than a predetermined threshold, then the transfer rate is re-calculated for the conductors requiring transfer rate adjustment as a function of SNR.