Abstract: A transition delay matching circuit in which the transition delay of the divided clock signal is substantially the same as the transition delay of the reference clock signal. The transition delay of the divided clock signal is adjusted by reducing the steady state amplitude of the divided clock signal. Apparatuses and methods for matching the transition delays of the divided clock signal and the reference clock signal are disclosed.

Abstract: A high-speed differential signaling logic gate includes a 1st input transistor, 2nd input transistor, complimentary transistor, current source, a 1st load, and a 2nd load. The 1st input transistor is operably coupled to receive a 1st input logic signal, which may be one phase of a first differential input signal. The 2nd input transistor is coupled in parallel with the 1st input transistor and is further coupled to receive a 2nd input logic signal, which may be one phase of a 2nd differential input signal. The complimentary transistor is operably coupled to the sources of the 1st and 2nd input transistors and to receive a complimentary input signal, which mimics the other phase of the 1st differential logic signal and the 2nd differential logic signal. The current source sinks a fixed current from the 1st and 2nd input transistors and the complimentary transistor. The 1st load is operably coupled to the drains of the 1st and 2nd input transistors to provide a 1st phase of a differential logic output.

Abstract: A method of providing synchronous transport of packets between asynchronous network nodes. An asynchronous network node capable of transmitting and receiving packetson the asynchronous network is designated as a master node. Each non-master asynchronous network node which desires to synchronously transport packets across the asynchronous network is designated as a slave node. Best arrival times for packets transmitted from slave nodes to the master node are communicated from the master node to the slave nodes. Bestpacket assembly times for packets to be transmitted by the particular slave node to the master node in the future for the packets to be received by the master node at future master clock referenced best arrival times are determined. Packets for transmission at slave nodes are prepared and transmitted according to determined future bestpacket assembly time information.

Abstract: A switch using indicators for address learning. The switch has a first activator configured to control a first indicator to indicate when a source address needs to be learned and when a source address has been learned. A second activator is configured to control a second indicator to indicate when a destination address has not been learned and when a destination address has been learned. Finally, a third activator is configured to control a third indicator to indicate when a source address has not been learned in all switches.

Abstract: The measuring of local oscillation leakage in radio frequency integrated circuits (RFICs) begins by concurrently enabling a transmitter portion and a receiver portion of a radio frequency integrated circuit. The processing then continues by providing a zero input to the transmitter portion such that information contained in the RF signals corresponds to local oscillation leakage produced by the transmitter portion. The processing continues by detecting the concurrent enablement of the transmitter and receiver portions. The processing continues by measuring, via the receiver portion, the received signal strength of the RF signals. The processing continues by processing the received signal strength over a predetermined period of time commencing upon the detection of the concurrent enablement to obtain a measure of the local oscillation leakage.

Abstract: A RFIC includes a die and a package. The die contains a radio frequency (RF) input/output (I/O) section, an RF-to-baseband conversion section, and a baseband processing section. The package includes a plurality of connections for connecting to the die. The die is positioned within the package to minimize adverse affects of parasitics components of coupling the RFIO section to an antenna. The positioning of the die within the package may be offset from the center of the package and/or positioned at the edge of the package.

Abstract: A method and system for combing requests for data bandwidth by a data provider for transmission of data over an asynchronous communication medium is provided. A headend receives one or more bandwidths requests from one or more cable modems via upstream communication. A scheduler then combines one or more bandwidths requests from the same cable modem to create a single data burst bandwidth. The headend then grants the data burst bandwidth to the appropriate cable modem via downstream communication.

Abstract: A method (and a computer accessible medium comprising one or more instructions which, when executed, implement the method) is contemplated. At least a first timing path is identified in a first timing report corresponding to a first partition of a circuit. For at least one timing constraint applied to the first timing path, a second timing path in a second partition of the circuit that causes the timing constraint is determined. A second timing report comprising the first timing path from the first timing report and the second timing path from the second partition is generated.

Abstract: A P-type metal oxide semiconductor (PMOS) device can include an N-well that does not extend completely throughout the active region of the PMOS device. For example, the PMOS device can be fabricated using a masking step to provide an N-well having an inner perimeter and an outer perimeter. The inner perimeter of the N-well surrounds at least a portion of the active region of the PMOS device. According to an embodiment, the inner perimeter of the N-well surrounds the entire active region. The PMOS device can include a deep N-well in contact with the N-well.

Abstract: The present invention includes an active pixel sensor that detects optical energy and generates an analog output that is proportional to the optical energy. In embodiments, the active pixel sensor can be implemented in a standard CMOS process, without the need for a specialized optical process. The active pixel sensor includes a reset FET, a photo-diode, a source follower, and a current source. The photo-diode is coupled to the source of the reset FET at a discharge node. The drain of the reset FET is couple to a power supply VDD. The discharge node is also coupled to the gate input of the source follower, the output of which is coupled to output node. In embodiments, shallow trench isolation is inserted between the active devices that constitute the photo-diode, the source follower, or the current source, where the shallow trench isolation reduces leakage current between these devices. As a result, dark current is reduced and overall sensitivity is improved.

Abstract: A power amplifier includes a transconductance stage, a cascode stage, and may include a signal level detection and bias determination module. The transconductance stage is operable to receive an input voltage signal and to produce an output current signal. The cascode stage communicatively couples to the transconductance stage and is operable to receive the output current signal and to produce an output voltage signal based thereupon. The cascode stage includes a Metal Oxide Silicon (MOS) transistor and a corresponding parasitic bipolar junction transistor, each of the gate of the MOS transistor and the base of the parasitic bipolar junction transistor available for voltage control. The signal level detection and bias determination module operably couples to the cascode stage and is operable to controllably bias the gate of the MOS transistor and to controllably bias the base of the corresponding parasitic bipolar junction transistor.

Abstract: A high-speed serial data transceiver includes multiple receivers and transmitters for receiving and transmitting multiple analog, serial data signals at multi-gigabit-per-second data rates. Each receiver includes a timing recovery system for tracking a phase and a frequency of the serial data signal associated with the receiver. The timing recovery system includes a phase interpolator responsive to phase control signals and a set of reference signals having different predetermined phases. The phase interpolator derives a sampling signal, having an interpolated phase, to sample the serial data signal. The timing recovery system in each receiver independently phase-aligns and frequency synchronizes the sampling signal to the serial data signal associated with the receiver. A receiver can include multiple paths for sampling a received, serial data signal in accordance with multiple time-staggered sampling signals, each having an interpolated phase.

Abstract: A method and system of processing sampled voice packets from a voice packet sender for transmission over a bit-rate sampled data transmission system, such as by a cable modem over a cable modem termination system, to a voice packet recipient. Unsolicited grant arrivals in response to a request from the voice packet sender coupled to the cable modem are determined. The storing of sampled voice packets is synchronized with the unsolicited grant arrivals. Upon receipt of an unsolicited grant arrival, currently stored sampled voice packets are transmitted to the cable modem for further transmission to the voice packet recipient over the cable modem termination system.

Abstract: A linear high powered integrated circuit transmitter includes an up-conversion module, a plurality of power amplifiers, balanced integrated circuit coupling, and a combining circuit. The up-conversion module is operably coupled to produce a differential up-converted signal by mixing one or more local oscillations with a low intermediate frequency (IF) signal. The balanced integrated circuit coupling couples the plurality of power amplifiers to the up-conversion module such that the power amplifiers amplify the up-converted signal to produce a plurality of amplified radio frequency (RF) signals. The combining circuit is operably coupled to combine the plurality of amplified RF signals to produce a transmit RF signal.

Abstract: A test head performs at-speed testing of high serial pin count gigabit per second (GBPS) devices. The test head includes a device under test (DUT) coupled to a first portion of the test head and a rider board coupled to the DUT. The rider board includes a first signal path including switching matrices coupled to the DUT, a second signal path including bit error rate testing (BERT) engines, each of the BERT engines being coupled to each other, corresponding ones of the switching matrices, and to the DUT, and a third signal path including Ethernet testing circuits coupled to the DUT. The BERT engines allow for routing of a test signal from any of the switching matrices to any other switching matrix (e.g., between non-adjacent switching matrices).

Abstract: An oscillator having multi-phase complementary outputs comprises a first plurality of single ended amplifiers connected in series to form an input and an output and a second plurality of single ended amplifiers connected in series to form an input and an output. The first and second plurality have the same odd number of amplifiers, A first feedback path connects the output to the input of the first plurality of amplifiers to establish oscillations in the first plurality of amplifiers at a frequency dependent upon the delay time from the input to the output of the first plurality. A second feedback path connects the output to the input of the second plurality of amplifiers to establish oscillations in the second plurality of amplifiers at a frequency dependent upon the delay time from the input to the output of the second plurality.

Abstract: A method for selectively deskewing data traveling through a bus in a network device is disclosed. Bit-level data is received from each data line of a plurality of data lines of the bus. Vertical line information is detected for the plurality of data lines to determine if there is a match with a training pattern. A skew distance is calculated once there is a match with the training pattern. Then, the plurality of data lines are bit aligned based on the skew distance.

Abstract: An apparatus for a multiplexor circuit includes a passgate circuit coupled to receive input signals and corresponding select signals comprising a subset of the input signals and select signals received by the multiplexor. The apparatus also includes a default circuit coupled to receive the select signals and coupled to an output node of the passgate circuit. If none of the select signals is asserted, the default circuit supplies a default voltage on the output node. Other passgate circuits and default circuits may be included coupled to other subsets of the input signals and select signals, and an output circuit may be included with inputs coupled to the output nodes of the passgate circuits. The default voltage may represent a logical value which allows the value from another passgate circuit to control the output of the output circuit.

Abstract: Certain embodiments of the invention may be found in, for example, a system that reduces noise in a substrate of a chip and may comprise a substrate and a first well disposed on top of the substrate. The first well may be a deep well. Notwithstanding, a second well and a third are both disposed within the first well and a first transistor may be disposed in the second well. A quiet voltage source may be connected to a body of the first transistor and a second transistor may be disposed in the third well. The first transistor may be a PMOS transistor and the second transistor may be an NMOS transistor. A noisy voltage source may be coupled to a source of the first transistor and a body of the first transistor may be resistively coupled to the second well.

Abstract: Presented herein is a system, method, and apparatus for decoding variable length codes. In one embodiment, there is presented a method for decoding variable length coded symbols. The method comprises storing one or more symbols from a plurality of variable length coded symbols in a first register; storing a portion of a particular symbol from the plurality of variable length coded symbols in the first register; storing another portion of the particular symbol in a second register; and storing the contents of the first register in memory after storing the portion of the particular symbol in the first register.