Abstract: A system and method are disclosed for efficiently generating a DVD compliant stream directly from an MPEG encoder. In a preferred embodiment of the invention, this is achieved by providing encoder microcode for generating a DVD standard protocol compliant stream directly from an analog signal according to DVD industry standards, such as DVD VOB. In this embodiment, the system and method of the present invention advantageously provide an encoder with the ability to generate a DVD VOB compliant stream without third party software intervention thus allowing for a more efficient and faster process for generating a DVD VOB compliant stream and for creating DVD disks from an analog source in real time. The present invention may also flexibly determine whether to output an MPEG compliant bit stream or a DVD VOB compliant stream or both.

Abstract: A small crystal oscillator with metal packaging includes a small size crystal oscillator circuit, a body encompassing the small size crystal oscillator circuit, first and second terminal leads coupled to the crystal oscillator circuit through the body, metal packaging encompassing at least a portion of the body, and a ground connection electrically coupled to the metal packaging. The invention includes a variety of shapes and configurations for the metal packaging and a variety of pin configurations.

Abstract: A test head performs at-speed testing of high serial pin count gigabit per second (GBPS) devices. The test head includes a device under test (DUT) coupled to a first portion of the test head and a rider board coupled to the DUT. The rider board includes a first signal path including switching matrices coupled to the DUT, a second signal path including bit error rate testing (BERT) engines, each of the BERT engines being coupled to each other, corresponding ones of the switching matrices, and to the DUT, and a third signal path including Ethernet testing circuits coupled to the DUT. The BERT engines allow for routing of a test signal from any of the switching matrices to any other switching matrix (e.g., between non-adjacent switching matrices).

Abstract: A signal processing system which discriminates between voice signals and data signals modulated by a voiceband carrier. The signal processing system includes a voice exchange, a data exchange and a call discriminator. The voice exchange is capable of exchanging voice signals between a switched circuit network and a packet based network. The signal processing system also includes a data exchange capable of exchanging data signals modulated by a voiceband carrier on the switched circuit network with unmodulated data signal packets on the packet based network. The data exchange is performed by demodulating data signals from the switched circuit network for transmission on the packet based network, and modulating data signal packets from the packet based network for transmission on the switched circuit network. The call discriminator is used to selectively enable the voice exchange and data exchange.

Abstract: A method and apparatus for generating a fifty percent duty cycle clock from a reference clock. The method and apparatus includes an edge generator, a controllable delay module, a duty cycle control loop module and a reset circuit. The edge generator is coupled to generate a clean edge of the reference clock. The controllable delay module is coupled to produce a delayed edge from the clean edge based on a duty cycle control signal. The duty cycle control loop module is coupled to generate the duty cycle control signal based on the delayed edge and the reference clock signals. The reset circuit is coupled to reset the edge generator to produce a second edge. The second edge is delayed by the controllable delay module to produce a second delayed edge such that the delayed edge and the second delayed edge constitute one period of the fifty percent duty cycle clock.

Abstract: An apparatus and a method for routing data in a radio data communication system having one or more host computers, one or more intermediate base stations, and one or more RF terminals organizes the intermediate base stations into an optimal spanning-tree network to control the routing of data to and from the RF terminals and the host computer efficiently and dynamically. Communication between the host computer and the RF terminals is achieved by using the network of intermediate base stations to transmit the data.

Abstract: A method and an apparatus for configuration of multiple context processing elements (MCPEs) are described. The method and an apparatus is capable of selectively transmitting data over a bidirectional shared bus network including a plurality of channels between pairs of MCPEs in the networked array. The method and an apparatus then selectively transmits a sideband bit indicating a direction in which the data is transmitted in the shared bus network.

Abstract: An apparatus is disclosed which includes a converter circuit and a noise suppression circuit. The converter circuit has a dynamic logic input, and is configured to generate a static logic output on an output node responsive to the dynamic logic input. The noise suppression circuit is coupled to receive a clock signal and is coupled to the output node. Responsive to a first phase of the clock signal, a precharge of a dynamic logic circuit generating the dynamic logic input occurs. The noise suppression circuit is configured to actively drive the static logic output on the output node responsive to the first phase. In some embodiments, the noise suppression circuit may reduce the noise sensitivity of the static logic output during the precharge phase, and may not impede operation of the converter circuit during the evaluate phase.

Abstract: A non-volatile memory cell (10) includes a charge-storing node (16). An electrically insulating first layer (76) is coupled between the node and a source of a first voltage (22). An electrically insulating second layer (66) is coupled between the node and a source of a second voltage (20–21). The area of the first layer is smaller than the area of the second layer. A controller (90) is arranged to cause the first voltage to be greater than the second voltage so that charge is extracted from the node and is arranged to cause the second voltage to be greater than the first voltage so that charge is injected into the node.

Abstract: An electrically and thermally enhanced die-up tape substrate ball grid array (BGA) package and die-up plastic substrate BGA package are described. A substrate that has a first surface and a second surface is provided. The stiffener has a first surface and a second surface. The second stiffener surface is attached to the first substrate surface. An IC die has a first surface and a second surface. The first IC die surface is mounted to the first stiffener surface. A plurality of solder balls is attached to the second substrate surface. In one aspect, a heat spreader is mounted to the second IC die surface. In another aspect, the stiffener is coupled to ground to act as a ground plane. In another aspect, the substrate has a window opening that exposes a portion of the second stiffener surface. The exposed portion of the second stiffener surface is configured to be coupled to a printed circuit board (PCB). In another aspect, a metal ring is attached to the first stiffener surface.

Abstract: An RF communications system includes a transmit node for transmitting an RF information signal and a receive node for receiving the transmitted RF information signal. The receive node includes a passive mixer coupled to an amplifier for producing an IF or baseband differential mixer output signal as a function of a LO drive signal. The passive mixer having a first plurality of transistors of a first polarity type arranged in a ring configuration and a second plurality of transistors of a second polarity type, wherein each of second plurality of transistors is coupled to one of the first plurality of transistors.

Abstract: Aspects of the invention provide a fast one level zero-current-state XOR gate. An embodiment of the invention provides a first pair of differentially configured transistors and a level shifting resistor coupled to the first pair of differentially configured transistors. The one level zero-current-state XOR gate may also include a second pair of differentially configured transistors. A core of the XOR gate may be coupled to outputs of the first and the second pairs of differentially configured transistors.

Abstract: A mobile communication device, such as a mobile telephone, that provides adaptive audible notifications to user. The mobile communication device is adapted to obtain information concerning the environment in which the device is located, such as ambient noise level or whether the device is in an enclosure, and to select an appropriate user notification loudness level based on the obtained information.

Abstract: A leading one correction circuit receives a significand from a floating point adder and a corresponding leading one prediction from a leading one predictor, and determines if the leading one prediction is correct. In one embodiment, the leading one prediction is a one hot vector having the same number of bits as the significand, with the set bit in the position predicted to have the leading one. In such an embodiment, the leading one correction circuit may perform a bitwise AND of the significand and leading one prediction, and the result of the bitwise AND may be ORed to generate a signal indicating whether or not the prediction is correct. In one implementation, the leading one correction circuit may operate concurrent with a shift of the significand in response to a shift amount indicated by the leading one prediction.

Abstract: A method and apparatus for generating a performance indicator in a high-speed communication system. A plurality of disparate communication status signals with differing formats from a transceiver are combined in a logic module to create a single link quality indicator signal. The link quality indicator signal is used to encode different operational states of the transceiver from fully operational, to marginally operational, to failed. The link quality indicator signal is advantageously employed to drive a LED creating a visual performance indicator.

Abstract: A memory management method that has the steps of assigning pointers to free memory locations and linking the pointers to one another creating a linked list of free memory locations having a beginning and an end. A free head pointer is assigned to a memory location indicating the beginning of free memory locations and a free tail pointer is assigned to a memory location indicating the end of free memory locations. An initial data pointer is assigned to the memory location assigned to the free head pointer and an end of data pointer is assigned to a last data memory location. The free head pointer is assigned to a next memory location linked to the last data memory location assigned to the end of data pointer. The next memory location indicates the beginning of free memory locations.

Abstract: A signal processing system which discriminates between voice signals and data signals modulated by a voiceband carrier. The signal processing system includes a voice exchange, a data exchange and a call discriminator. The voice exchange is capable of exchanging voice signals between a switched circuit network and a packet based network. The signal processing system also includes a data exchange capable of exchanging data signals modulated by a voiceband carrier on the switched circuit network with unmodulated data signal packets on the packet based network. The data exchange is performed by demodulating data signals from the switched circuit network for transmission on the packet based network, and modulating data signal packets from the packet based network for transmission on the switched circuit network. The call discriminator is used to selectively enable the voice exchange and data exchange.

Abstract: A cache comprises a memory including a plurality of entries and a circuit. Each entry of the plurality of entries is configured to store a cache block. The circuit is configured to select a first entry of the plurality of entries to store a first cache block. In one implementation, the first cache block corresponds to a first transaction initiated by a first agent, wherein the first entry is selected from a first subset of the plurality of entries indicated as selectable for the first agent. In another implementation, the circuit is configured to select the first entry of the plurality of entries in response to whether the first cache block is a remote cache block or a local cache block. In other implementations, the circuit may be configured to handle a combination of the above.

Abstract: An exemplary embodiment of the present invention described and shown in the specification and drawings is a transceiver with a receiver, a transmitter, a local oscillator (LO) generator, a controller, and a self-testing unit. All of these components can be packaged for integration into a single IC including components such as filters and inductors. The controller for adaptive programming and calibration of the receiver, transmitter and LO generator. The self-testing unit generates is used to determine the gain, frequency characteristics, selectivity, noise floor, and distortion behavior of the receiver, transmitter and LO generator. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or the meaning of the claims.

Abstract: A method for selecting frame encoding parameters to improve transmission performance for a transmitting frame being transmitted from a transmitting station to a receiving station over a transmission medium of a frame-based communications network is provided, the transmitting frame having a header segment and a payload segment, the header segment being transmitted using a fixed set of encoding parameters such that the header segment can be received and decoded by all stations on the network, the payload segment being transmitted using a variable set of payload encoding parameters, the transmitting station sending the transmitting frame using one set of the variable set of payload encoding parameters at a time. The receiving station receives and decodes the header and payload segments of each transmitting frame. The decoding includes computing frame statistics. A plurality of sets from the variable set of payload encoding parameters are selected to form a possible set of payload encoding parameters.