Abstract: Method and apparatus for determining the stopping point of an iterative decoding process. In one embodiment the estimated values of an iteration of an iterative decoder are provided to a signature circuit. If the signature does not differ from the previous signature developed from a prior iteration, or the signature developed from an iteration prior to the previous iteration, the decoding stops. The variance may also be tested and compared to a threshold as a criteria to stop the iterative decoding.

Abstract: A low voltage current mirror circuit (also referred to as a bias circuit) for establishing a plurality of bias voltages from an input current supplied to an input terminal of the circuit includes an input stage, a current stage connected to the input stage, a feedback stage connected to the current stage, a reference bias stage connected to the feedback stage and the current stage. The circuit establishes first and second bias voltages suitable for biasing current sources of a first type, and third and fourth bias voltages suitable for biasing current sources of a second type complementary to the first type. The bias voltages track the input current over variations in at least one of process, temperature and power supply voltage.

Abstract: A method and apparatus are provided for implementing an enhanced reduced memory mode (RMM) of decoding HDTV MPEG-2 video stream. In one instance, the RMM mode is adaptively enabled with up/down conversion by using the picture-type information. In another instance, the RMM mode is provided by performing anchor-frame compression/decompression by using adaptive DPCM technique with picture-type information. The quantization (PCM) tables are generated using the Lloyd algorithm. Further, the predictor for each pixel is determined by a use of the Graham rule.

Abstract: A lock-detect circuit is configured to detect whether an incoming signal has acquired a lock to a reference signal using a first frequency detect window and to detect whether the incoming signal has lost a previously acquired a lock to the reference signal using a second frequency detect window different from the first frequency detect window. The two signals are applied to two different down-counters that are first synchronized before initiating the count-downs. If the offset between the counts of the two counters is less than the first frequency detect window, the incoming signal is detected as having acquired a lock to the reference signal. If the offset between the counts of the two counters is greater than the second frequency detect window, the incoming signal is detected as having lost its previously acquired lock to the reference signal.

Abstract: Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C3MOS) logic fabricated in conventional CMOS process technology. An entire family of logic elements including inverter/buffers, level shifters, NAND, NOR, XOR gates, latches, flip-flops and the like are implemented using C3MOS techniques. Optimum balance between power consumption and speed for each circuit application is achieve by combining high speed C3MOS logic with low power conventional CMOS logic. The combined C3MOS/CMOS logic allows greater integration of circuits such as high speed transceivers used in fiber optic communication systems. The C3MOS structure enables the use of a power supply voltage that may be larger than the voltage required by the CMOS fabrication process, further enhancing the performance of the circuit.

Abstract: A method for determining differential delay of at least two bonded links is described. The method comprises a step of providing, on the part of a transmitting entity, at least some of the data packets transmitted from the transmitting entity to a receiving entity with time stamps, the time stamps indicating a point of time when a respective data packet has been generated, and a step of deriving a propagation delay from a time stamp of a data packet and a time of arrival of the data packet at a receiving entity. The method further comprises a step of determining a differential delay of a link from the propagation delay of the link and a propagation delay of a reference link.

Abstract: Typical communication systems operate with a single channel decoder, and hence would have to settle for the performance from the single channel decoder regardless of the conditions of the communications channel. The present invention uses a hybrid channel decoder comprising multiple channel decoders, each configured to optimize the quality of the re-constructed signal for different channel conditions. Therefore, the desired decoder can be selected as conditions of the communications channel, or the data signal, change over time, so as to optimize the re-constructed data signal. In embodiments, the data signal is a speech signal.

Abstract: A tester unit for evaluating data integrity of a block of data is described. The tester unit comprises a checksum determination facility adapted for deriving a checksum value from a block of data stored in a memory, and a checksum evaluation facility adapted for comparing the derived checksum value with a predetermined checksum value, and for initiating a reload of the block in case the derived checksum value differs from the predetermined checksum value.

Abstract: A blanking interval information decoder is described, with the blanking interval decoder being adapted for decoding blanking interval information transmitted in a video signal. The blanking interval information decoder comprises a processing unit, a memory adapted for storing at least one of code and data, and a set of blanking interval decoding routines stored in the memory. Each of the blanking interval decoding routines is adapted for decoding a certain type of blanking interval information of a certain video standard.

Abstract: The invention refers to a video data processing system and a video data processing circuit, comprising at least two functional blocks of which at least a first functional block is programmable so that different functions can be provided by said first functional block.

Abstract: The invention relates to a method comprising the steps of: (a) providing of software code written in a non-proprietary software program language; and (b) compiling said software code into a software code written in a different, proprietary software program language, wherein said compiled software code is of a first format; and (c) parsing said compiled software code to transform it to a second format.

Abstract: A card includes in a radio transceiver that communicates in first and second frequency bands. First and second antennas are in the card and are coupled to the radio transceiver. A microprocessor in the card selects one of the first and second antennas.

Abstract: A method and apparatus for adaptively controlling a variable gain amplifier (VGA). The operation of the VGA is separated into a low gain mode and a high gain mode and the mode in which the VGA is currently operating in is adaptively sensed. A threshold voltage is compared to a control voltage of the VGA; if the VGA is currently operating in the low gain mode and the control voltage is higher than the threshold voltage, the VGA is switched from the low gain mode to the high gain mode; and if the VGA is currently operating in the high gain mode and the control voltage is lower than the threshold voltage, the VGA is switched from the high gain mode to the low gain mode.

Abstract: A network device including at least one network port, a clock, address resolution logic (ARL) tables, and address resolution logic. The clock generates a timing signal. The ARL tables are configured to store and maintain data related to port addresses of the network device. The address resolution logic is coupled to the ARL tables and the clock, and configured to search the ARL tables and to perform learning concurrently during alternating slots of the timing signal. Upon receiving a data packet at the at least one port, the address resolution logic is configured to search the ARL tables for a destination address based on the data packet. When the destination address is found, the address resolution logic is configured to update a related record of the ARL tables based on the learning, the address resolution logic configured to perform searches and updates.

Abstract: A signal processing system which discriminates between voice signal and data signals modulated by a voiceband carrier. The signal processing system includes a voice exchange, a data exchange and a call discriminator. The voice exchange is capable of exchanging voice signals between a switched circuit network and a packet based network. The signal processing system also includes a data exchange capable of exchanging data signals modulated by a voiceband carrier on the switched circuit network with unmodulated data signal packets on the packet based network. The data exchange is performed by demodulating data signals from the switched circuit network for transmission on the packet based network, and modulating data signal packets from the packet based network for transmission on the switched circuit network. The call discriminator is used to selectively enable the voice exchange and data exchange.

Abstract: A method for enhancing the bit rate and/or margin at which quadrature amplitude modulation (QAM) communication is performed over multiple bands of a communication link includes the steps of varying a spectral allocation and constellation size with which communication is performed, so as to define a combination of spectral allocation and constellation size at which the bit rate and/or margin are enhanced. The rate adaptation method identifies the spectral allocation and constellation size to use on each of the multiple bands that results in a total bit rate greater than or equal to the target bit rate, subject to specified constraints on SNR margin and/or BER limits. If more than one parameter set has this property, the rate adaptation method may for example select the spectral allocation and constellation size combination that maximizes the minimum SNR margin across the multiple bands.

Abstract: An on-chip inductor may be fabricated by creating at least one dielectric layer, creating at least one conductive winding on the at least one dielectric layer and creating: (1) a P-well layer having a major surface parallel to a major surface of the dielectric layer, (2) field oxide layer having a major surface parallel to a major surface of the dielectric layer, (3) P-well and field oxide layer, or (4) a poly-silicon layer having a major surface parallel to a major surface of the dielectric layer.

Abstract: A system and method for noise cancellation in a signal-processing circuit (e.g., an analog-to-digital converter circuit). Various aspects of the present invention may comprise inputting a first input signal and a digital input signal to the signal-processing circuit. The digital input signal may, for example, comprise a digital dither signal or other processor control signal. The signal-processing circuit may, for example, output a signal comprising a first signal component that is primarily a function of the first input signal and a second signal component that is primarily a function of the digital input signal. The second signal component may be estimated based on estimated behavior of the signal-processing circuit in response to the digital input signal. The estimated second signal component may, for example, be substantially removed from the signal-processing circuit output signal.

Abstract: A divider module for use in an oscillation synthesizer includes a plurality of flip-flops and a logic circuit. The plurality of flip-flops is interoperably coupled to produce a divider value based on a control signal. The logic circuit is operably coupled to produce the control signal based on divider select signals. Each of the plurality of flip-flops includes a first differential latch module, a second differential latch module. The first differential latch module is operably coupled to produce a differential latched signal based on a differential flip-flop input signal. The second differential latch module is operably coupled to produce a differential flip-flop output based on the differential latched signal. Each of the first and second differential latch modules includes a sample transistor section, a hold transistor section, a first gating circuit, and a second gating circuit.

Abstract: A radio frequency (RF) integrated circuit (IC) includes a local oscillation module, analog radio receiver, analog radio transmitter, digital receiver module, digital transmitter module, and digital optimization module. The local oscillation module is operably coupled to produce at least one local oscillation. The analog radio receiver is operably coupled to directly convert inbound RF signals into inbound low intermediate frequency signals based on the local oscillation. The digital receiver module is operably coupled to process the inbound low IF signals in accordance with one of a plurality of radio transceiving standards to produce inbound data. The digital transmitter is operably coupled to produce an outbound low intermediate frequency signal by processing outbound data in accordance with the one of the plurality of radio transceiving standards. The analog radio transmitter is operably coupled to directly convert the outbound low IF signals into outbound RF signals based on the local oscillation.