Abstract: A system is provided for correcting start-up deficiencies in an amplifier. The system includes a comparing device configured to (i) receive a second circuit node voltage and a reference voltage as inputs, (ii) compare the received second circuit node voltage and the reference voltage, and (iii) produce a compensating voltage signal based upon the comparison. Next, an active device has a control terminal connected to an output port of the comparing device and is configured to receive the compensating voltage signal. The active device also includes an output terminal connected to the control terminal of the second active device, and a common terminal connected to a first circuit node. Another active device has a control terminal connected to the output port of the comparing device and is configured to receive the compensating voltage signal. The other active device also has an output terminal connected to the control terminal of the first active device, and a common terminal connected to the first circuit node.

Abstract: Provided is a switched capacitor feedback circuit including two or more input ports configured to receive a corresponding a number of input signals and at least one output port. The output port is configured to output an adjusting signal. The input signals includes a number of primary signals and two or more reference signals that are associated with a first timing phase of operation. The adjusting signal is produced based upon a comparison between the primary signals the reference signals. Also provided is a pair of active devices having gates coupled together and structured to receive the adjusting signal. The active devices are configured to provide a gain to the adjusting signal in accordance with a predetermined gain factor, and facilitate an adjustment to the number of primary signals based upon the gain during a second timing phase of operation.

Abstract: Systems and methods that provide directional prefetching are provided. In one embodiment, a method may include one or more of the following: storing a first block and a second block in a prefetch buffer; associating a first block access with a backward prefetch scheme; associating a second block access with a forward prefetch scheme; and, if the first block is accessed before the second block, then performing a backward prefetch with respect to the first block.

Abstract: A bias filtering module with at least two capacitive levels satisfies both a settle time requirement and a filtering requirement using a voltage dependent filter module whose capacitance is a function of a voltage potential on the filtering circuitry output terminal. The final capacitance level is approximately three times larger than the initial capacitance level. MOS capacitors having a voltage dependent charge capacity within the bias filtering module are coupled between a plurality of bias lines and circuit common. In an alternate embodiment, a selectable first group of capacitors are switched into connection within the bias filtering module as a second group of capacitors approximately reach a fully charged state within a specified settle time to provide improved filtering.

Abstract: A method and system described for producing frequency multiplication/division by any non-integer output signal frequency relative to a reference signal frequency of a Phase Lock-Loop (PLL), while simultaneously maintaining low jitter. In one embodiment, the invention increases the number of the available clock phases to M and then shifts the output clock phase by one, every K/M cycle. In one aspect of the present invention, this is accomplished by adding a multiplexer (MUX) to the output of the PLL to implement the phase shifting every K/M cycles. In another aspect, the MUX is placed in the feedback loop of the PLL. In one embodiment, a quantizer is used to drive the MUX.

Abstract: A power efficient and reduced electromagnetic interference (EMI) emissions multi-transmitter system for unshielded twisted pair (UTP) data communication applications. For each transmitter, digital transmit data is converted to a current-mode differential signal analog waveform by a digital-to-analog converter (DAC). The output current from each DAC is used to generate the required transmit voltage on the respective UTP line. Timing circuitry staggers the time base of each transmitter to reduce the aggregate EMI emissions of the multi-transmitter system.

Abstract: Methods and systems for controlling delay relatively independent of process, supply-voltage, and/or temperature (“PVT”) variations include sensing an output signal after a number of inverters and activating different numbers of transistors and/or adjusting strength of transistors in a delay path to compensate for PVT variations. In an embodiment, a waveform is received, delayed, and output to an output terminal using at least one relatively low-power device. Supplemental output power is provided by at least one relatively high-power device until the output waveform exceeds a threshold.

Abstract: Disclosed herein is a method and system for providing a secondary communication channel overlaid on a primary communication channel using an enhanced encoding method to effectively expand the utilized information capacity of the primary communication channel. Aspects of the invention may include encoding a portion of at least a first word of one or more data packets in a datastream. A running disparity of the encoded word may be reversed. Hence, if an encoded running disparity of an encoded word is RD positive, i.e., RD(+), then the running disparity is reversed to RD negative, i.e., RD(?). Similarly, if an encoded running disparity is RD negative, i.e., RD(?), then the running disparity is reversed to RD positive, i.e., RD(+). The word may be a data word, control word, or an idle word corresponding to a data packet, a control packet, and an idle packet, respectively.

Abstract: Methods and apparatuses for spectrally shaping mismatch errors in a multi-bit digital to analog converter (DAC). In an embodiment, the multi-bit DAC is constructed from K separate multi-element sub-DACs, where K and the number of elements in each sub-DAC are each preferably greater than two. A received digital input code is split into a set of K sub-codes corresponding to the digital input code. The set of K sub-codes can have one of at least N different sub-code orders that specify an order of each of the K sub-codes with respect to one another, where N>2. A sum of the K sub-codes equals the digital input code. One of the at least N different sub-code orders is selected using a shuffling algorithm. Then, each sub-code in the set of K sub-codes is output in accordance with the selected sub-code order.

Abstract: Aspects of the invention provide a fast one level zero-current-state XOR gate. An embodiment of the invention provides a first pair of differentially configured transistors and a level shifting resistor coupled to the first pair of differentially configured transistors. The one level zero-current-state XOR gate may also include a second pair of differentially configured transistors. A core of the XOR gate may be coupled to outputs of the first and the second pairs of differentially configured transistors.

Abstract: There is disclosed a technique in which any peaks above a threshold level are reduced, but not clipped, such that the effects of such peaks is reduced. Although the implementation of the technique preferably includes a clipping step, it is performed on the front-end rather than as the last step in the technique, such that the output signal is not a clipped signal. Any noise introduced by the clipping step, so-called clipping noise, is preferably filtered out of the useful frequency band of the signal.

Abstract: A method and system for performing combing for PAL chroma data for a display having a plurality of lines is disclosed. The display is capable of depicting a frame including a horizontal boundary having a top edge and a bottom edge. The top line of the plurality of lines is at the top edge of the horizontal boundary, while a bottom line of the plurality of lines is at the bottom edge of the horizontal boundary. The method and system include replacing bottom line chroma data with previous line chroma data for the top line. The method and system also include replacing top line chroma data with subsequent line chroma data for the bottom line. The method and system can also provide three-line combing chroma data for a remaining portion of the plurality of lines.

Abstract: An integrated circuit formed on a semiconductor chip, comprising a low pass filter circuit having a first resistor of a first resistance value and a capacitor of a first capacitance value, wherein the first resistance value and the first capacitance value determine a corner frequency of the filter; and a tuning circuit having a second resistor of a second resistance value, a switched-capacitor of a third resistance value and a comparator that compares two voltage signals to produce a control signal, wherein the control signal adjusts the first and second resistance values as a function of the third resistance value. The corner frequency of the filter can be adjusted by varying one or more reference voltage signals. In combination, the corner frequency of the filter is adjusted by changing the frequency of a clock that controls the switched-capacitor to decrease the circuit sensitivity.

Abstract: An electrically and thermally enhanced die-up ball grid array (BGA) package is described. An integrated circuit (IC) package includes a first substrate, a second substrate, and a stiffener. A surface of the first substrate is attached to a first surface of the stiffener. A surface of the second substrate is attached to a second surface of the stiffener. An IC die may be attached to a second surface of the second substrate or to the second surface of the stiffener. Additional electronic devices may be attached to the second surface of the second substrate.

Abstract: A high precision charge pump used in a phase-lock-loop incorporating a phase/frequency detector is designed and constructed to substantially eliminate the effects of DC offset and glitch errors on the charge pump output current. The high precision charge pump is constructed of parallel current paths each having a central node which is, in turn, connected to a feedback element. The feedback element defines a feedback current which is applied to the charge pump so as to maintain the two central nodes at an equi-potential level and to maintain the value of the pump-down current exactly equal to the value of the pump-up current output by the device.

Abstract: A method is provided for testing buffer memory. The method includes a step of testing a buffer memory having a plurality of memory locations including redundant memory locations, to determine if any of the plurality of memory locations are unusable. Next, an address of an unusable memory location of the plurality of memory locations is determined. Next, the address of the unusable memory location is stored. Next, a use of the unusable memory location is prevented based on the stored address of the unusable memory location.

Abstract: A method for controlling operation of a multi-pair gigabit transceiver. The multi-pair gigabit transceiver comprises a Physical Layer Control module (PHY Control), a Physical Coding Sublayer module (PCS) and a Digital Signal Processing module (DSP). The PHY Control receives user-defined inputs from the Serial Management module and status signals and diagnostics signals from the DSP and the PCS and generates control signals, responsive to the user-defined inputs, the status signals and diagnostics signals, to the DSP and the PCS.

Abstract: The present invention relates to a system and method for processing the read and write operations in a memory architecture. The system processing the read and write operations includes at least one local memory block and a synchronously controlled global controller coupled to the local memory block and adapted to extend the high portion of a clock pulse. The method for processing the read and write operations includes skewing a clock pulse using at least one word line interfacing with the global controller.

Abstract: A resonant oscillator circuit includes an active device and a resonator that causes the active device to oscillate at a resonant frequency of the resonator. The active device includes one or more transistors that are DC biased using one or more resistors. The bias resistors generate thermal noise that is proportional to the resistance value. An external inductor circuit is connected across the output terminals of the active device and in parallel with the resonator. The external inductor circuit shorts-out at least some of the thermal noise that is generated by the bias resistors, and thereby reduces the overall phase noise of the resonant oscillator.

Abstract: A computing device operates over a range of voltages and frequencies and over a range of processor usage levels. The computing device includes at least a variable frequency generator, a variable voltage power supply and voltage supply level and clocking frequency management circuitry. The variable frequency generator is coupled to the processor and delivers a clock signal to the processor. The variable voltage power supply is coupled to the processor and delivers voltage to the processor. The voltage supply level and clocking frequency management circuitry adjust both the voltage provided by the variable voltage power supply and the frequency of the signal provided by the variable frequency generator. The computing device includes a temperature sensor that provides signals indicative of the temperature of the processor and the voltage supply level and clocking frequency management circuitry adjusts the voltage and/or the clocking frequency provided by the variable voltage power supply.