Abstract: Method and circuitry for converting a differential logic signal to a single-ended logic signal eliminate slower PMOS transistors and speed up the conversion process. In specific embodiments differential logic signals of the type employed in, for example, current-controlled complementary metal-oxide-semiconductor (C3MOS) logic are converted to single-ended rail-to-rail CMOS logic levels using a differential pair of NMOS transistors with resistors as load devices and an NMOS current source transistor that provides dynamically adjusted tail current.

Abstract: A CMOS gain stage includes biasing circuitry configured to insure saturation of a subsequent stage without a source follower circuit. The CMOS gain stage is optionally powered by a supply voltage that is greater than a permitted supply voltage for a processes technology that is used to fabricate the CMOS gain stage. In order to protect CMOS devices within the CMOS gain stage, optional drain-to-bulk junction punch-through protection circuitry is disclosed. A variety of optional features can be implemented alone and/or in various combinations of one another. Optional features include process-voltage-temperature (“PVT”) variation protection circuitry, which renders a gain relatively independent of process, voltage, and/or temperature variations. Optional features further include bandwidth enhancement circuitry.

Abstract: A plurality of groups of first flip-flops (group 40 of flip-flops A1-An?1 for each of channels CIA-CIC) store input data clocked in response to first clock signals (A-C). First enable signals (Stack_en) are generated for each group of first flip-flops. A plurality of groups of second flip-flops (group 60 of flip-flops B1-Bn for each of channels CIA-CIC) store the input data from the first flip-flops in response to the first enable signals and first clock signals. A second enable signal (Slide_en) is generated in response to a second clock signal (D) and the first enable signal. A plurality of groups of third flip-flops (group 80 for each of channels CIA-CIC) store the data in response to the second enable signal and second clock signal. The data is transmitted in serial form at the rate of the second clock signal.

Abstract: A graphics integrated circuit chip is used in a set-top box for controlling a television display. The graphics chip processes analog video input, digital video input, a graphics input and an audio input simultaneously. The system may use anti-aliased text and graphics to provide high quality display of graphical elements, or glyphs, which represent an image of a character of text or graphics, on television and other displays. The graphical elements may be superimposed over live video or arbitrary graphics imagery.

Abstract: A system and method for facilitating the authentication of wireless devices in an environment with multiple wireless networks. A user wishing to join an operating wireless network can bring his wireless device within close physical proximity, for example, less than one meter, of a device in the network that he wishes to join. The user then presses an authenticate button, which causes both devices to enter a low transmission power mode. In such case, the devices are only capable of operation within the close proximity. Being in low power mode will diminish the possibility of eavesdropping on the authentication process. Power down mode also reduces the amount of message traffic in the area and saves scarce power and processing resources at the nodes, which are now out of range. Authentication then takes place in low power mode and once completed, both devices resume normal power levels and continue communicating normally.

Abstract: A radio card, such as a PCMCIA card, received by an electronic device has a first interface coupling radio circuitry within the radio card to the electronic device. The radio card also has a second interface, independent of the first interface, that couples with an antenna disposed within the electronic device upon receipt of the radio card by the electronic device. The second interface may comprise a plurality of antenna contacts located along tracks of the electronic device used to aid reception of the radio card. A second and possibly external antenna may also automatically couple with the second interface upon insertion. By selective placement of the antenna contacts on the radio card, a specific one of the antennas may be selected. Otherwise, internal switching circuitry supports antenna diversity or simultaneous use of a plurality of antennas.

Abstract: Embodiments of the invention may provide a method for implementing an adaptive multimode media queue. A mode of operation may be determined for a received media stream based on a sampling rate of the media stream. The mode of operation may be a wideband mode and/or a narrowband mode. Depending on the determined mode, the adaptive multimode media queue may be partitioned into a low band media queue and a high band media queue. A wideband media stream split into a high band and a low band is buffered into the adaptive multimode media queue wherein the high band is stored in the high band media queue, and the low band is stored in the low band media queue. The high band media queue and low band media queue may be a contiguous memory block within the adaptive multimode media queue. The received media stream, which may have different sampled data rates may be buffered within the partitioned adaptive multimode media queue.

Abstract: The present invention is a method and a system for controlling a voltage at a node in a circuit such that the node is prevented from having an unknown floating voltage during a steady state of a clock signal. The circuit includes a transmission gate which has input and output terminals, and operates in response to a clock signal. The node is located proximal to the output terminal of the transmission gate. The method includes the operations of driving the node with an input signal when the transmission gate is open during a first steady state of the clock signal and pulling the node to a fixed voltage when the transmission gate is closed during a second steady state of the clock signal.

Abstract: Requests are processed to transmit data packets upstream from a cable modem to a cable headend in a manner that minimizes the use of CPU operations and/or memory capacity. Data packets to be transmitted upstream are stored at the cable modem. The data packets each have a given transmission data byte length value. Burst profiles are received successively at the cable modem. Each time a new bust profile is received, a set of physical data length values corresponding to respective transmission data byte length values is calculated from the parameters of the received burst profile. The calculated set of physical data length values is stored in memory so the individual values can be retrieved from the transmission data byte length values again and again, rather than being re-calculated each time a conversion is made from transmission data byte length values to physical data length values. The same set of physical data length values is used until a new burst profile is received by the cable modem.

Abstract: A method for refreshing data in a circuit element included in a dynamic register. A static loop is coupled to the circuit element as a feedback path from the output terminal to the input terminal of the circuit element. A control signal is provided to the static loop. The static loop is activated via the control signal to refresh the data in the circuit element.

Abstract: A power supply multiplexing circuit including a first supply voltage input. A first pair of cascoded PMOS transistors are in series with the first supply voltage input. A first native NMOS transistor is in series with the first pair of cascoded PMOS transistors. Also, a second supply voltage input and a second pair of cascoded PMOS transistors are in series with the second supply voltage input; and a second native NMOS transistor in series with the second pair of cascoded PMOS transistors. The gates of the first and second native NMOS transistors are driven by two control signals out of phase with each other, and sources of the first and second native NMOS transistors are connected together to output an output voltage.

Abstract: An integrated oscillator that may be used as a time clock includes circuitry that oscillates about an RC time constant, which RC time constant is adjustable to provide a desired frequency of oscillation. More specifically, the oscillator includes a capacitor array that has a plurality of capacitors coupled in parallel wherein each capacitor may be selectively included into the RC time constant or selectively excluded there from. Rather than setting the capacitance values to a desired capacitance value, a system for adjusting the time constant includes circuitry for measuring an output frequency and for comparing that to a certified frequency source wherein the time constant is adjusted by adding or removing capacitors from the capacitor array until the frequency of the internal clock matches an expected frequency.

Abstract: A design of integrated circuit components to prevent accidental turn on when large input signals are accepted. With integrated circuits operated at lower power supply voltages, input signals having large peak values can tend to turn on devices within the integrated circuit erroneously. By placing amplifiers within the integrated circuits where input signals are received and removing the power of such amplifiers, accidental turn on can be minimized.

Abstract: A system for receiving signals (e.g., optical signals) includes an input device, an amplification device, and a feedback device. The amplification device receives a signal from the input device and includes a transimpedance portion. The transimpedance portion includes a first section having a plurality of elements (e.g., resistors and transistors) and a second section having a plurality of elements (e.g., resistors and transistors). One or more of the elements (e.g. transistors or resistors) in the first and second sections are mismatched to introduce a systematic offset in the transimpedance stage, to make the net input referred offset of the amplification device unidirectional. The feedback device (e.g. an integrator) is coupled to an output of the amplification device and an input of the transimpedance portion to provide a unidirectional offset correction to the amplification device for reduced noise enhancement.

Abstract: An apparatus for providing a programmable gain attenuator (PGA) while minimizing the influence of semiconductor switches on the signal being attenuated. An example apparatus comprises a impedance ladder with taps forming the junctions between impedances the PGA is then programmed by grounding the taps through terminating resistors.

Abstract: A magnetic interface generator generates a magnetic interface at a center frequency f0. The magnetic interface generator is a passive array of spirals that are deposited on a substrate surface. The magnetic interface is generated in a plane at a distance Z above the surface of the substrate. The distance Z where the magnetic interface is created is determined by the cell size of the spiral array, where the cell size is based on the spiral arm length and the spacing S between the spirals. The center frequency of the magnetic interface is determined by the average track length DAV of the spirals in the spiral array. In embodiments, the spiral array is one sub-layer in a multi-layer substrate. The spacing S of the spiral array is chosen to project the magnetic interface to another layer in the multi-layer substrate so as to improve performance of a circuit in the plane of the magnetic interface.

Abstract: A low-complexity sampling rate conversion (SRC) method and apparatus for the processing of digital audio signals. A first stage upsamples an input audio signal to generate an upsampled audio signal. For example, the first stage may perform 1:2 upsampling using a halfband filter. A second stage re-samples the upsampled audio signal from the first stage at a target sampling rate. For example, re-sampling may be achieved using linear interpolation.

Abstract: System and method for processing communication signals in a communication system having a detector for detecting a parameter of a communication signal. A communication signal is provided to a non-linear processor (NLP) adapted to examine the signal and to decide whether or not to enter an active state based upon a parameter of the signal. If the NLP enters an active state, the NLP performs non-linear processing on the signal. The NLP communicates to the detector whether the NLP is active or inactive. If the NLP is active, a processing step of the detector is disabled.

Abstract: A printed circuit board includes two differential signal traces, a layer of core material, a layer of filler material, and a ground plane. The filler material is replaced by an air core under the differential signal traces.

Abstract: A reduced emission transmitter may include an encoder block, which may be partitioned into a first group comprising odd encoder processing cells and a second group comprising even encoder processing cells. A DAC block may also be partitioned into a first group comprising odd DAC processing cells and a second group comprising even DAC processing cells. The first group of encoder processing cells may be coupled to the first group of DAC processing cells and the second group of encoder processing cells may be coupled to the second group of DAC processing cells. The first group of encoder processing cells may be clocked using a first clock signal and the second group of encoder processing cells may be clocked using a second clock signal, the second clock signal being a delayed version of the first clock signal.