Abstract: A scan interface for an integrated circuit includes a scan clock and a scan mode signal. The scan mode signal is indicative of whether or not scan is active, and may be used by dedicated scan circuitry in integrated circuit. Such circuitry may be inactive if the scan mode indicates that scan is inactive, and active if the scan mode indicates that scan is active. For example, the scan circuitry may not toggle is scan is inactive. The scan circuitry may present a reduced load to functional circuitry if scan is inactive. In some embodiments, static and dynamic scan circuits are included for use with static and dynamic logic circuits, respectively.

Abstract: An output buffer includes first and second circuit portions coupled between input and output terminals. Each circuit portion includes a capacitive element; an output transistor having a gate coupled to the capacitive element, and a drain that drives a voltage at the output terminal; and a current generator configured to generate a charging current that is directed to the capacitive element responsive to a logic transition at the input terminal, wherein the charging current causes a substantially linear ramp voltage to form at the gate of the output transistor, whereby the ramp voltage controls a slew rate of the output terminal voltage.

Abstract: A K-bit information signal represented by a polynomial U(x) having a degree K?1 is received. The information signal is transformed to form a transformed information signal using a first transform represented by a polynomial G1(x) having a degree P. The transformed information signal is represented by a polynomial T(x) having a degree K+P?1. T(x) equals U(x)G1(x). An initial cyclic code represented by a polynomial R1(x) is generated for the transformed information signal using a second transform represented by a polynomial G2(x), where G2(x) has high-order leading-zero terms. R1(x) equals the remainder obtained by dividing T(x) by G2(x). The initial cyclic code is transformed to form a final cyclic code represented by a polynomial R2(x) using the first transform. R2(x) equals R1(x)/G1(x).

Abstract: Often programmable gain attenuators (PGAs) are combined with high pass filters. Adjustment of the highpass filter however can have unintended effects, such as changing the step size of the PGA. By placing the resistance of the highpass filter in parallel with a programmable attenuator divider, the steps of the PGA can be minimally affected as the highpass frequency is adjusted.

Abstract: An antenna includes a magnetic interface generator that generates a magnetic interface at a center frequency f0. The magnetic interface generator is a passive array of spirals that are deposited on one layer of a multi-layer substrate. The magnetic interface is generated in a plane at a distance Z above the surface of the substrate layer that it is printed on, where the antenna in printed on a second layer of the multi-layer substrate. The distance Z where the magnetic interface is created is determined by the cell size of the spiral array, where the cell size is based on the spiral arm length and the spacing S between the spirals. The center frequency of the magnetic interface is determined by the average track length DAV of the spirals in the spiral array. The spacing S of the spiral array is chosen to project the magnetic interface to the second layer in the multi-layer substrate so as to improve performance of the antenna that printed on the second layer.

Abstract: Training signals can be chosen based on stored prior connection information to reduce the use of extra tones in transmitted training signals and thereby improve receiver performance. By choosing training signals based on the stored prior connection information, it is possible to make the training signals indirectly a function of the loop impairments. One advantage of this scheme is that we can choose to omit certain tones in the training signals, based on previous connection information, on a loop-by-loop basis. For example, in an ADSL Transceiver Unit-Central office end (ATU-C) device, per-local-loop prior connection information may be employed to select DMT tones to be included in downstream training signals. Similarly, in an ADSL Transceiver Unit-Remote terminal end (ATU-R) device, prior connection information may be employed to select DMT tones to be included in upstream training signals.

Abstract: A system for generating multiple synthesized clocks having an input terminal for receiving a reference signal, a phase locked loop circuit coupled to the input signal terminal, where the phase locked loop circuit is capable of generating a plurality of output signals that are frequency locked to the reference signal and having a plurality of different phases, a phase rotator coupled to the phase locked loop circuit, where the phase rotator generates an even greater plurality of phases.

Abstract: An integrated receiver with dual channel transport stream decoding and delivery substantially implemented on a single CMOS integrated circuit is described. For multiple channel transfers to hard disk drive storage, a multiplexed IDE host interface is provided with shared pins for data, address, and chip-select lines of the IDE interface so that multiple hard drives may be interfaced using the common pins of the integrated circuit.

Abstract: A frequency dividing circuit divides a master clock frequency by a non-integer factor to provide an output clock signal whose frequency is equal to the frequency of the master clock signal divided by that non-integer factor. In one embodiment, the circuit is operative to divide the master clock frequency by 2.5.

Abstract: A first MOS-on-NWELL device is formed on a substrate and has its pickup terminals optionally connected together. A second MOS-on-NWELL device is formed on the substrate and has its pickup terminals optionally connected together. A gate of the first MOS-on-NWELL device is connected to the pickup terminals of the second MOS-on-NWELL device. A gate of the second MOS-on-NWELL device is connected to the pickup terminals of the first MOS-on-NWELL device. A first PMOS transistor is formed on a substrate and has its source and drain terminals connected together. A second PMOS transistor is formed on a substrate and has its source and drain terminals connected together. A gate of the first PMOS transistor is connected to the source and drain terminals of the second PMOS transistor. A gate of the second PMOS transistor is connected to the source and drain terminals of the first PMOS transistor.

Abstract: An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programable attenuation and a programable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors with shields to increase circuit Q. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator.

Abstract: An exemplary embodiment of the present invention described and shown in the specification and drawings is a transceiver with a receiver, a transmitter, a local oscillator (LO) generator, a controller, and a self-testing unit. All of these components can be packaged for integration into a single IC including components such as filters and inductors. The controller for adaptive programming and calibration of the receiver, transmitter and LO generator. The self-testing unit generates is used to determine the gain, frequency characteristics, selectivity, noise floor, and distortion behavior of the receiver, transmitter and LO generator. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or the meaning of the claims.

Abstract: Methods and systems for improved feedback processing in delta-sigma modulators, including single bit and multi-bit delta-sigma modulators, continuous-time and discrete-time delta-sigma modulators, and digital and/or analog feedback loops. One or more processes are performed in a pipeline having a higher throughput rate than a throughput rate of a delta-sigma modulator. Any of a variety of processes and combinations of processes can be performed in the pipeline including, without limitation, quantization, digital signal processing, and/or feedback digital-to-analog conversion.

Abstract: An RF antenna coupling structure includes a first transformer, a second transformer, and a transformer balun. The first transformer includes a primary winding and a secondary winding, wherein the primary winding of the first transformer is operably coupled to a power amplifier, and wherein the secondary winding of the first transformer has a desired output impedance corresponding to the operational needs of the power amplifier. The second transformer includes a primary winding and a secondary winding, wherein the primary winding of the second transformer is operably coupled to a low noise amplifier, and wherein the secondary winding of the second transformer has a desired output impedance corresponding to the needs of the low noise amplifier. The transformer balun includes a differential winding and a single-ended winding, wherein the differential winding is operably coupled to the secondary windings of the first and second transformers and the single-ended winding is operably coupled to an antenna.

Abstract: Presented herein are a system(s), method(s), and apparatus for detecting and recovering from false synchronization. False synchronization can be detected on the fly through either on an interrupt-driven basis or polling-driven basis. The number of incorrect checksums is compared to the number of uncorrectable errors detected. If the number of incorrect checksums is large compared to the number of uncorrectable errors detected, resynchronization occurs.

Abstract: A network device is provided which includes a device input, at least one port, a frequency doubler, a data I/O device, and a programmable delay locked loop. The frequency doubler is coupled to the input and configured to receive an input signal and output an output signal having double the frequency of the input signal. The data I/O device is configured to output data based upon a reference clock signal. The programmable delay locked loop is coupled to the device input and configured to receive an input signal and to automatically output an output signal being a predetermined amount out of phase from the input signal. An external clock signal received at the device input is input to the frequency doubler. The output of the frequency doubler is input to the data I/O device as a reference clock. Data (e.g., from internal device logic) is output from the data I/O device to the at least one port.

Abstract: A system for connecting multiple repeaters into a single collision domain comprising a first repeater, a second repeater and a stacking bus. The first repeater has a plurality of network ports. The second repeater also has a plurality of network ports. The stacking bus connects the first repeater and the second repeater and is configured to relay status signals between the first and said second repeaters.

Abstract: An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programable attenuation and a programable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator.

Abstract: A token-based receiver diversity processing is described. In one embodiment, a receiver diversity comprises repeaters receiving wirelessly transmitted packets from a mobile station, and one of the repeaters forwarding packets of the wirelessly transmitted packets to a switch if the one repeater is currently assigned to forward packets from the mobile station based on an indicator assigned prior to the wirelessly transmitted packets being sent.

Abstract: A method and system of executing computer instructions is described. Each instruction defines first and second operands and an operation to be carried out on said operands. Each instruction also contains an address field of a predetermined bit length which identifies a test register holding a plurality of test bits greater than the predetermined bit length. The test register holds a test code defining a test condition. The test condition is checked against at least one condition code and the operation is selectively carried out in dependence on whether the condition code satisfies the test condition. In one embodiment, the condition codes are set on a lane-by-lane basis for packed operands.