Abstract: A digital IF demodulator includes an analog-to-digital (A/D) converter that receives an analog IF signal and converts it to a digital IF signal. A parallel multiplier then down-converts the digital IF signal to a baseband signal having a video component and an audio component. The frequency down-conversion uses a parallel multiplier driven by an outer feedback loop that corrects gross frequency errors in said digital IF signal. The digital IF demodulator also includes a video recovery circuit that selects the video component from the baseband signal and further down-converts the baseband signal to a video baseband using a video complex mixer driven by an inner feedback loop that corrects fast phase perturbations in the video recovery circuit. Finally, the digital IF demodulator includes an audio recovery circuit that (i) receives said baseband signal from the parallel multiplier, and (ii) down-converts the audio component to an audio baseband signal using an audio complex mixer.

Abstract: A memory-efficient convolutional interleaver/deinterleaver with a memory array, a write commutator, and a read commutator wherein the commutators perform their respective write and read operations relative to a preselected memory cell after a predetermined delay. The delay is chosen using a modulo-based technique, such that an efficient implementation of a Ramsey Type-II interleaver is realized.

Abstract: A method for designing multi-layer electronic circuits includes defining a plurality of circuit blocks in terms of physical boundaries, the plurality of circuit blocks including a first circuit block with at least one port for connecting to a portion of inter-block routing having conducting material external to the first circuit block. The method further provides protective routing for the at least one port of the first circuit block in a region between the block and the inter-block routing, wherein circuitry within the first circuit connected to the at least one port is not in-circuit with the conducting material of the inter-block routing during processing steps involving the conducting material. The protective routing is a conducting layer which is higher in the multi-layer structure than the highest conducting layer used for routing the net containing the at least one port for inter-block routing.

Abstract: An integrated fuse has regions of different doping located within a fuse neck. The integrated fuse includes a polysilicon layer and a silicide layer. The polysilicon layer includes first and second regions having different types of dopants. In one example, the first region has an N-type dopant and the second region has a P-type dopant. The polysilicon layer can also include a third region in between the first and second regions, which also has a different dopant. During a fusing event, a distribution of temperature peaks around the regions of different dopants. By locating regions of different dopants within the fuse neck, agglomeration of the silicide layer starts reliably within the fuse neck (for example, at or near the center of the fuse neck) and proceeds toward the contact regions. An improved post fuse resistance distribution and an increased minimum resistance value in the post fuse resistance distribution is realized compared to conventional polysilicon fuses.

Abstract: Provided is a circuit to convert input CMOS level signals having a predetermined duty cycle to CML level signals having a higher duty cycle. The circuit includes two differential transistor pairs connected together. The two differential pairs are constructed and arranged to use gates of the associated transistors as inputs to receive and combine a number of phase shifted CMOS input signals. The combined CMOS input signal are converted to CML level signals which are provided as circuit outputs.

Abstract: A method for flexibly configuring default values of a network device through an EEPROM interface is disclosed. A header is received from an EEPROM through the EEPROM interface and it is determined from the header whether any default value of the network device should be updated, and if any, how many should be updated. At least one configuration instruction is fetched from the EEPROM when it is determined that the network device should be updated. The at least one configuration instruction is interpreted and a register default value of the default values corresponding to the interpreted at least one configuration instruction is changed.

Abstract: Methods and systems for controlling delay relatively independent of process, supply-voltage, and/or temperature (“PVT”) variations include sensing an output signal after a number of inverters and activating different numbers of transistors and/or adjusting strength of transistors in a delay path to compensate for PVT variations. In an embodiment, a waveform is received, delayed, and output to an output terminal using at least one relatively low-power device. Supplemental output power is provided by at least one relatively high-power device until the output waveform exceeds a threshold.

Abstract: A memory access system is described which generates two memory addresses from a single memory access instruction which identifies a register holding at least two packed objects. In the preferred embodiment, the contents of a base register is combined respectively with each of two or more packed objects in an offset register.

Abstract: A system and operation of the system for improvement of transmitter and receiver frequency accuracy for a local radio communication unit that communicates digital data with a remote communication unit. In the local unit, received signals are down-converted into complex baseband digital samples by A/D conversion. A downlink digital phase rotator applies a fine frequency shift in accordance with a receiver frequency offset command. The resultant baseband signal is used by the data demodulator and by a receiver frequency error estimator to obtain receiver frequency errors. A data modulator generates baseband complex samples which are shifted in carrier frequency by an integrated uplink digital phase rotator in accordance with a transmitter frequency offset command. The modulated samples are then converted by a D/A converter and upconverted in frequency for transmission to the remote unit.

Abstract: The present invention is directed to a sigma-delta digital to analog converted (DAC) including a digital-sigma delta modulator, a decimation filter, and a multi-bit DAC. The digital sigma-delta modulator receives a digital input signal and produces a quantized digital signal therefrom. The decimation filter receives the quantized digital signal and produces a decimated digital signal therefrom. The multi-bit DAC receives the decimated digital signal and produces an analog output signal therefrom. The analog output signal is representative of the digital input signal.

Abstract: The present invention comprises an apparatus and corresponding method for performing a built-in self-test (BIST) of a data communications system. The apparatus of the invention includes a transmitter, a receiver coupled to the transmitter and a test control system coupled to the transmitter and receiver for measuring a data error rate of the data communications system. The transmitter, receiver and test control system are disposed on a common substrate, such as an integrated circuit.

Abstract: A system includes a bus and a circuit for precharging the bus. The circuit may be coupled to receive a clock signal associated with the bus, and may be configured to precharge a bus during an interval of the period of the clock signal, the interval being between a first edge (rising or falling) and the subsequent edge (falling or rising). A second interval within the period and excluding the interval may be used to perform a bus transfer. In this manner, both precharging and transfer may be performed in the same clock cycle. Bandwidth of the bus may be improved since transfers may occur each clock cycle, rather than having a non-transfer clock cycle for precharging.

Abstract: A non-volatile memory cell (10) includes a charge-storing node (16). An electrically insulating first layer (76) is coupled between the node and a source of a first voltage (22). An electrically insulating second layer (66) is coupled between the node and a source of a second voltage (20-21). The area of the first layer is smaller than the area of the second layer. A controller (90) is arranged to cause the first voltage to be greater than the second voltage so that charge is extracted from the node and is arranged to cause the second voltage to be greater than the first voltage so that charge is injected into the node.

Abstract: An integrated communications system. Comprising a substrate having a receiver disposed on the substrate for converting a received signal to an IF signal. Coupled to a VGA for low voltage applications and coupled to the receiver for processing the IF signal. The VGA includes a bank pair having a first bank of differential pairs of transistors and a second bank of differential pairs of transistors. The bank pair is cross-coupled in parallel, the IF signal is applied to the bank pair decoupled from a control signal used to control transconductance output gain of the bank pair over a range of input voltages. A digital IF demodulator is disposed on the substrate and coupled to the VGA for low voltage applications, for converting the IF signal to a demodulated baseband signal. And a transmitter is disposed on the substrate operating in cooperation with the receiver to establish a two way communications path.

Abstract: A novel method and interface is provided for conducting read data transfers between an initiator device on a single-transaction bus and a target device on a split-transaction bus. Embodiments of the present invention permit the initiator device to “post” a read request for a specified amount of data from a specified address on the split-transaction bus to an interface that resides between the single-transaction bus and the split-transaction bus. The requested read data is then retrieved over the split-transaction bus and presented in a high-speed memory within the interface for direct access by the initiator device over the single-transaction bus. Latency is avoided because the initiator device is not required to wait for the emergence of the requested read data from the split-transaction bus but, instead, may continue to perform other activities on the single-transaction bus and then obtain the requested read data at a later time.

Abstract: A signal processing system which discriminates between voice signals and data signals modulated by a voiceband carrier. The signal processing system includes a voice exchange, a data exchange and a call discriminator. The voice exchange is capable of exchanging voice signals between a circuit switched network and a packet based network. The signal processing system also includes a data exchange capable of exchanging data signals modulated by a voiceband carrier on the circuit switched network with unmodulated data signal packets on the packet based network. The data exchange is performed by demodulating data signals from the circuit switched network for transmission on the packet based network, and re-modulating data signal packets from the packet based network for transmission on the circuit switched network. The call discriminator is used to selectively enable the voice exchange and data exchange.

Abstract: A plurality of CMTS devices are linked together and synchronized to facilitate communication between the respective CMTS devices and respective downstream cable modems. According to one embodiment of the invention, one of the CMTS devices is designated as a master device, and the other CMTS devices are designated as slave devices. The respective CMTS devices are connected to each other by means of a synchronization bus. The master CMTS device then generates and broadcasts a future time stamp value, which is received by the respective slave CMTS devices. When the time stamp counter in the master CMTS device reaches the transmitted value, a control signal is broadcast over the synchronization bus. The slave CMTS devices then retrieve the time stamp value and reset their respective local time stamp counters to the received value. In this manner, the CMTS devices are synchronized.

Abstract: An improved dither generation circuit and method for digital audio circuits generates pseudo-random numbers that are then interpreted as 2's complement numbers representing data points of a bipolar signal. The random number signal is high-pass filtered to reduce the energy contained in the audio band. The resulting dither signal is applied to the circuit in its main feedback loop and is effective to prevent idle tones. Because of its spectrally shaped characteristic this dither signal introduces less noise into the audio band of interest and thereby improves the overall signal-to-noise ratio of the audio circuit.

Abstract: An integrated circuit includes electrical components that include one or more electrical elements on one or more dielectric layers. The electrical element has a geometric shape that exceeds prescribed integrated circuit manufacturing limits in at least one dimension. To achieve compliance with foundry rules, the electrical element is fabricated to include a non-conducting region that negligibly effects the electrical characteristics. The non-conducting region includes a hole, a series of holes, a slot and/or a series of slots spaced within the electrical element at dimensions that are less than the integrated circuit manufacturing limits.

Abstract: A network device including a memory, a queue management unit, a memory management unit, and a search switching unit. The memory includes a plurality of memory banks. The queue management unit is configured to receive a plurality of search requests and to prioritize the search requests. The memory management unit is coupled to the queue management unit and the memory, and is configured to initiate a plurality of binary searches based on the plurality of search requests. Each binary search is executed simultaneously in different banks of the plurality of memory banks. The search switching unit is coupled to the memory and the memory management unit, and is configured to switch each binary search from one memory bank of to another memory bank after a predetermined number of search steps are performed by each binary search.