Abstract: A method of and device for performing a data expansion operation on a plurality of input data objects to generate expanded output data objects is disclosed. The method comprises receiving and decoding a data manipulation instruction defining a data expansion operation, a portion of the data manipulation instruction indicating an expansion operation from a number of predetermined types of data manipulation operations. The method includes generating one or more expansion objects responsive to the indication of an expansion operation, said expansion objects being for use in extending an input data object. The input data objects are manipulated according to control information expansion objects programmed to produce a set of expanded output data objects.

Abstract: In a low-pass filter for a phase locked loop (PLL) circuit, a capacitor formed by an N-type substrate, a P-type region formed on the N-type substrate, a thick oxide formed over the P-type region, a P+ gate electrode formed over the thick oxide and coupled to a first voltage supply line, and P+ pick-up terminals formed in the P-type region adjacent the gate electrode and coupled to a second voltage supply line, whereby a gate-to-substrate voltage is maintained at less than zero volts to maintain a stable control voltage for the PLL.

Abstract: A predictive time base generator having predictive synchronizer and replica delay element coupled with the synchronizer feedback delay loop. The predictive time base generator receives a clock signal delayed by a predetermined clock delay and produces a predictive time signal advanced in time by an amount represented by the replica delay element. The replica delay element can replicate one or both of a predetermined clock delay and a predetermined data delay, substantially nullifying the respective delays in critical signal paths of a device. The replica delay element can include replicas of structure(s) found in an incoming clock path and an outgoing data path, such elements including, for example, voltage level shifters, buffers or data latches, multiplexers, wire element models, and the like. A predictive computer bus interface adapter which incorporates the aforementioned predictive time base generator also is provided.

Abstract: A communications system, having a combination Reed-Solomon encoder and a Turbo-Code encoder Data frame configuration which may be changed to accommodate embedded submarkers of known value are embedded in with the data order to aid synchronization in the receiver system, by providing strings of known symbols. The string of known symbols may be the same as the symbols within a training header that appears at the beginning of a data frame. Frame parameters may be tailored to individual users and may be controlled by information pertaining to receivers, such as bit error rate, of the receiver. Additional headers may be interspersed within the data in order to assist in receiver synchronization. Frames of data may be acquired quickly by a receiver by having a string of symbols representing the phase offset between successive header symbols in the header training sequence in order to determine the carrier offset.

Abstract: Calibration of received signal strength indication (RSSI) within a radio frequency integrated circuit (RFIC) begins by concurrently enables a transmitter portion and receiver portion. With both the transmitter and receiver enabled, the RFIC provides a zero input to the transmitter portion, where the zero input is an effective zero input based on the input circuitry of the transmitter portion. The RFIC then measures, via the receiver portion, the received signal strength of the RF signal generated by the transmitter portion regarding the zero input signal. The RFIC then compares the measured received signal strength with a desired zero input signal strength value. If the measured received signal strength compares unfavorably with the desired zero input signal strength value (e.g.

Abstract: Circuitry to remove switches from signal paths in integrated circuit programmable gain attenuators. Programmable gain attenuators and programmable gain amplifiers commonly switch between signal levels using semi-conductor switches. Such switches may introduce non-linearities in the signal. By isolating the switches from the signal path linearity of the PGA can be improved.

Abstract: A circuit and method for bridging an analog signal between two integrated circuits operating at different supply voltages. The circuit is a two stage fixed gain amplifier. The first stage is a transconductance amplifier and the second stage is an operational amplifier. The first stage converts an input signal from a voltage into a current. The second stage converts the current signal to an output voltage signal.

Abstract: A ring oscillator circuit, such as a VCO, with a relatively high level of noise rejection for noise originating from both the voltage supply and ground. The ring oscillator circuit is composed of a plurality of differential delay circuits, each differential delay circuit generating a differential output signal that is a delayed (and preferably inverted) version of a differential input signal. ‘Each differential delay circuit includes first and second input transistors for receiving the differential input signal. Each differential delay circuit also includes first and second load transistors coupled in parallel with the respective first and second input transistors. Each differential delay circuit further includes a first current source coupled between the first input transistor and a first power supply terminal (e.g.

Abstract: A system and method of creating a highly efficient digital amplifier which can take either analog or digital inputs, and produce a high power accurate representation of the input to drive speakers or other low impedance load is described. The system employs a transition detector and delay unit which allows the comparator of the signal modulator to ignore its inputs for a pre-determined number of subsequent clock cycles once an output transition has been detected. Through the use of faster clocks and variable clock cycle skips upon the comparator's output transition, finer resolution of the feedback's clock period for noise-shaping purposes is achieved. Finer resolution of the clock period allows the present invention to employ a more aggressive noise-shaping than previously possible.

Abstract: A CABAC decoding engine is devised to cover all aspects of decoding all CABAC-coded syntax elements for AVC. This CABAC decoding engine acts like a Co-processor to another Processor (CPU), which guides the decoding of the bit stream. The CABAC decoding engine or Co-processor has the following highlights: unique context model retrieving and storing method is developed to allow a complete syntax element to be decoded in one hardware (H/W) execution cycle (not necessarily one clock cycle.); H/W assisted approach is provided to accelerate context model initialization; H/W based approach is incorporated to allow fast de-binarization; H/W based approach is provided to allow a block of syntax elements to be decoded instead of one by one; and dedicated H/W accelerators are incorporated to decode special syntax elements.

Abstract: Embodiments of the present invention perform logical operations utilizing a symmetric logic circuit comprising two logic units. In a symmetric logic circuit, the circuit configuration used to process a first logic input in the first logic unit is the same as the circuit configuration used to process a second logic input in the second logic unit, and the circuit configuration used to process the second logic input in the first logic unit is the same as the circuit configuration used to process the first logic input in the second logic unit.

Abstract: A communications receiver architecture characterized by a relatively low intermediate frequency (IF) and a polyphase filter. The receiver includes an input amplifier coupled to a carrier signal. Respective I and Q demodulators are coupled to the output of the input amplifier. A quadrature local oscillator (LO) generator provides respective LO_I and LO_Q inputs to the I demodulator and LO_Q inputs to the I demodulator and to the Q demodulator. The quadrature LO generator is driven by a phase-locked LO, and the LO frequency is such that an IF of, in one embodiment, approximately 1 MHz results. The I demodulator and Q demodulator outputs are applied through respective AID converters to a polyphase filter. The polyphase filter outputs are then processed by a digital I/Q demodulator.

Abstract: An apparatus and a method for routing data in a radio data communication system having one or more host computers, one or more intermediate base stations, and one or more RF terminals organizes the intermediate base stations into an optimal spanning-tree network to control the routing of data to and from the RF terminals and the host computer efficiently and dynamically. Communication between the host computer and the RF terminals is achieved by using the network of intermediate base stations to transmit the data.

Abstract: A method and apparatus for searching an electronically stored table of information including a plurality of table entries and facilitating high speed searching of a table to provide a longest matching entry. The table searching method uses at least one memory unit having a table of information including a plurality of data entries. The table of information has a plurality of search keys associated with the plurality of data entries and the plurality of search keys form a tree structure based on a prefix length for each of the search keys. The plurality of search keys are expanded such that each of the plurality of search keys has two lowest level search keys associated therewith that cover a lowest level of the tree structure. A binary search of the lowest level search keys is performed based on a search value to determine a longest prefix match. A data entry of the plurality of data entries is output based on said longest prefix match.

Abstract: A filter settings generation operation includes sampling colored noise present at the input of a receiver to produce a sampled signal. The sampled signal is spectrally characterized across a frequency band of interest to produce a spectral characterization of the sampled signal. This spectral characterization may not include a signal of interest. The spectral characterization is then modified to produce a modified spectral characterization. Filter settings are then generated based upon the modified spectral characterization. Finally, the input present at the receiver is filtered using the filter settings when the signal of interest is present to whiten colored noise that is present with the signal of interest. In modifying the spectral characterization, pluralities of spectral components of the spectral characterization are independently modified to produce the modified spectral characterization. Modifications to the spectral characterization may be performed in the frequency domain and/or the time domain.

Abstract: A system and method of assembling a ball grid array (BGA) package with IC die support is described. A stiffener is attached to a substrate that includes a centrally located opening with an integrated circuit (IC) die support structure removably held therein. An IC die is mounted to a central region of the stiffener. Further assembly process steps may be performed on the BGA package with IC die support. The IC die support structure is removed from the centrally located opening. In aspects of the invention, the IC die support structure is removably held in the opening by an adhesive tape or by one or more substrate tabs.

Abstract: A direct conversion radio frequency (RF) tuner includes a mixer generating I and Q quadrature components. A phase detection circuit generates a phase error measurement between the I quadrature component and the Q quadrature component. A phase correction circuit corrects a phase of the Q component based on the phase error measurement, and outputs a phase-corrected Q quadrature component. An I quadrature component gain control circuit receives the I quadrature component and outputting an amplitude corrected I quadrature component. A Q quadrature component gain control circuit receives the phase corrected Q quadrature component and outputs an amplitude corrected Q quadrature component.

Abstract: A method and an apparatus for configuration of multiple context processing elements (MCPEs) are described. According to one aspect of the invention, the structure that joins the MCPE cores into a complete array in one embodiment is actually a set of several mesh-like interconnect structures. Each interconnect structure forms a network, and each network is independent in that it uses different paths, but the networks join at MCPE input switches. The network structure of one embodiment of the present invention is comprised of a local area broadcast network (level 1), a switched interconnect network (level 2), a shared bus network (level 3), and a broadcast network. In one embodiment, the level 3 network is used to carry configuration data for the MCPEs while the broadcast network is used to carry configuration data for the level 3 network drivers and switches. In one embodiment, the level 3 network is bidirectional and dynamically routable.

Abstract: Methods and systems for limiting power supply and ground bounce enables control of the output current drive dependent on the changes in supply (VDD and GND) levels. This is made possible by making the gate drive of the output driver PMOS and NMOS dependent on the VDD and GND swings. When the VDD or GND increases above normal operating levels, the gate drive of the output driver PMOS is reduced and when the GND or VDD reduces below normal operating levels, the gate drive of the output driver NMOS is reduced. This leads to reduced current flow between the supplies and the pad thereby reducing the VDD and GND bounce problem.

Abstract: Driver circuits of the present invention provide current to drive laser diodes. The output current of the driver circuit includes a data signal and a low frequency tone signal. The low frequency tone signal is within the bandwidth of a power control feedback loop. The tone signal introduces low frequency noise into the output signal of the driver circuit. The low frequency noise causes jitter at the zero crossing points of the driver circuit output signal. A laser driver circuit of the present invention provides a compensation current to a laser diode. The compensation current is out of phase with the tone signal. The compensation current eliminates the low frequency noise in the output signal of the laser driver circuit.