Abstract: LDPC (Low Density Parity Check) coded modulation symbol decoding. Symbol decoding is supported by appropriately modifying an LDPC tripartite graph to eliminate the bit nodes thereby generating an LDPC bipartite graph (such that symbol nodes are appropriately mapped directly to check nodes thereby obviating the bit nodes). The edges that communicatively couple the symbol nodes to the check nodes are labeled appropriately to support symbol decoding of the LDPC coded modulation signal. The iterative decoding processing may involve updating the check nodes as well as estimating the symbol sequence and updating the symbol nodes. In some embodiments, an alternative hybrid decoding approach may be performed such that a combination of bit level and symbol level decoding is performed. This LDPC symbol decoding out-performs bit decoding only. In addition, it provides comparable or better performance of bit decoding involving iterative updating of the associated metrics.

Abstract: A method for making a memory cell for reducing the cost and complexity of modifying a revision identifier (ID) or default register values associated with an integrated circuit (IC) chip, and a method for manufacturing the same. The cell, which may be termed a “Meta-Memory Cell” (MMCEL), is implemented on metal layers only and utilizes a dual parallel metal ladder structure which traverses and covers each metal and via layer from the bottom to the top of the metal layer structure of the chip. One of the metal ladders is connected to a power supply at the bottom metal layer, corresponding to a logic 1, and another metal ladder is connected to ground at the bottom metal layer, corresponding to a logic 0. The output of the MMCEL can thus be inverted at any metal or via layer and can be inverted as often as required. Significant cost savings are achieved because a revision ID or default register bits may be modified by altering only those metal layers where design changes are necessary.

Abstract: A memory cell circuit for modification of a default register value in an integrated circuit chip, which includes a plurality of metal layers and first and second supply potentials. The circuit comprises a memory cell, a register and a control circuit. The memory cell has a first metal interconnect structure that traverses the plurality of metal layers using a first plurality of vias, wherein the first metal interconnect structure is coupled to one of the first and second supply potentials, a second metal interconnect structure that traverses the plurality of metal layers using a second plurality of vias, wherein the second metal interconnect structure is coupled to the other one of the first and second supply potentials, and an output, wherein a state of the output is programmable by altering any one of the plurality of metal layers or any one of a plurality of via layers. The register has a data input, a data output and control inputs. The control circuit is coupled to the control inputs of the register.

Abstract: A system and method are used to determine connectivity and/or cable faults of a cable. A signal transmitting and receiving system is coupled to the cable. An analog-to-digital converter (ADC) coupled to the signal transmitting and receiving system. A TDR system coupled to the ADC and a memory, and a controlling system coupled to at least one of the ADC, the TDR system, and the signal receiving and transmitting system. The controlling system includes a controller and one or more state machines that are used to control the TDR system.

Abstract: A feedforward filter has a plurality of feedforward filter taps, including a feedforward filter reference tap. The reference tap of the feedforward filter is positioned proximate a center position of the feedforward filter. A ramping circuit assembly has an input port configured to receive at least one decision feedback filter tap coefficient from a decision feedback filter. A coefficient ramping circuit is configured to provide a ramped output for at least one of the decision feedback filter tap coefficients. The ramped output is varied over time from a first value to a second value. The second value is dependent upon the value of a decision feedback filter tap coefficient. An output port of the ramping circuit assembly is configured to communicate information representative of the ramped output(s) to a precoder.

Abstract: A memory cell for reducing the cost and complexity of modifying a revision identifier (ID) or default register values associated with an integrated circuit (IC) chip, and a method for manufacturing the same. The cell, which may be termed a “Meta-Memory Cell” (MMCEL), is implemented on metal layers only and utilizes a dual parallel metal ladder structure that traverses and covers each metal and via layer from the bottom to the top of the metal layer structure of the chip. One of the metal ladders is connected to a power supply at the bottom metal layer, corresponding to a logic 1, and another metal ladder is connected to ground at the bottom metal layer, corresponding to a logic 0. The output of the MMCEL can thus be inverted at any metal or via layer and can be inverted as often as required. Significant cost savings are achieved because a revision ID or default register bits may be modified by altering only those metal layers where design changes are necessary.

Abstract: A modifiable circuit for coupling at least two adjacent logic blocks in an integrated circuit chip is disclosed. The chip includes a plurality of metal layers and first and second power supply potentials. The circuit comprises a first and second metal interconnect structures, and an interconnect. The first metal interconnect structure traverses the plurality of metal layers using a first plurality of vias, wherein the first metal interconnect structure is located at a boundary of the at least two adjacent logic blocks. The second metal interconnect structure traverses the plurality of metal layers using a second plurality of vias, wherein the second metal interconnect structure is located at the boundary of the at least two adjacent logic blocks.

Abstract: A network interface is presented that receives packet data from a shared medium and accomplishes the signal processing required to convert the data packet to host computer formatted data separately from receiving the data packet. The network interface receives the data packet, converts the analog signal to a digitized signal, and stores the resulting sample packet in a storage queue. An off-line processor, which may be the host computer itself, performs the signal processing required to interpret the sample packet. In transmission, the off-line process converts host-formatted data to a digitized version of a transmission data packet and stores that in a transmission queue. A transmitter converts the transmission data packet format and transmits the data to the shared medium.

Abstract: A method of processing sampled voice packets from a voice packet sender for transmission over a bit-rate sampled data transmission system, such as by a cable modem over a cable modem termination system, to a voice packet recipient. Unsolicited grant arrivals in response to a request from the voice packet sender coupled to the cable modem are determined. The storing of sampled voice packets is synchronized with the unsolicited grant arrivals. Upon receipt of an unsolicited grant arrival, currently stored sampled voice packets are transmitted to the cable modem for further transmission to the voice packet recipient over the cable modem termination system.

Abstract: A low power supply band-gap current reference includes a 1st P-N junction device, a 2nd and P-N junction device, a 1st current source, a 2nd current source, a 1st resistor, a 2nd resistor, a 3rd resistor, an operational amplifier, and a current mirror. The 1st and 2nd P-N junction devices are operably coupled to the 1st and 2nd current sources, respectively. The 2nd P-N junction device is a larger device than the 1st P-N junction device. The 2nd resistor is operably coupled in parallel with the 1st P-N junction device and the 2nd resistor is coupled in series with the 2nd P-N junction device. The 3rd resistor is coupled in parallel with the series combination of the 2nd resistor and 2nd P-N junction device. The operational amplifier is coupled to control the 1st and 2nd current sources based on the voltage imposed across the 1st and 2nd resistors. The current mirror is operably coupled to mirror the current of the 1st and/or 2nd current source to provide a band-gap reference current.

Abstract: A mechanism and method for redefining an application specific integrated circuit's I/O bus structure in real-time. The mechanism includes an address map block, a state machine block, and a bus arbitration block. At initialization, the address map is configured to divide the address space into regions and type of bus structure. When an I/O access is requested by a client (e.g., CPU, DMA controller, etc.), the request is mapped into a region and type of bus structure by the address map block. The region and type of bus structure is used by the state machine. The state machine determines the syntax and protocol for the region and type of bus. The state machine signals the bus arbitration block to grant I/O bus ownership when it is available. Once ownership is granted, I/O bus pins are defined and access is granted.

Abstract: The modulation format of a data block (frame) received from a servicing base station by a wireless terminal in a cellular wireless communication system is identified. This involves first receiving several radio frequency (RF) bursts ofone data block (frame) from the servicing base station. The RF burst carries a number of modulated symbols. The training sequence is extracted from the RF burst and is made of a number of modulated symbols. The training sequences are first processed assuming a first modulation format to produce a first accumulated channel energy. Then, the training sequences are processed assuming a second modulation format to produce a second accumulated channel energy. The first and second accumulated channel energies are compared to determine which accumulated channel energy is greater. The modulation format of the data block is identified as the modulation format corresponding to the greater accumulated channel energy.

Abstract: A method for selecting a mode of operation for at least two modems is described. First, a handshake procedure is performed in order to determine a set of possible modes of operation supported by said modems. From said set of possible modes of operation, a set of favorable modes of operation is derived. In case there exist two or more favorable modes of operation, a probing-based selection is performed that comprises evaluating respective performances of said favorable modes of operation. The favorable mode of operation with the best performance is selected as a resultant mode of operation.

Abstract: An analog to digital converter includes an array of differential input amplifiers. Each amplifier inputs an input voltage and a corresponding voltage reference, and outputs a differential signal representing a comparison of the input voltage and the corresponding voltage reference. A plurality of latches stores the differential signal from each of the differential input amplifiers. A decoder converts the stored differential signals to N-bit digital output. A first interface amplifier is connected to a first edge amplifier of the array through a first cross point. A second interface amplifier is connected to a second edge amplifier of the array through a second cross point. The first interface amplifier and the second interface amplifier are connected to each other through a third cross point.

Abstract: A demodulator (10) converts television signals to video baseband signals and audio baseband signals including stereo signals representing a right channel signal value, a left channel signal value and a pilot signal having an amplitude. A DSP (60) recursively finds a coefficient value for scaling that keeps the pilot signal amplitude within a range of values, there by improving baseband signal quality, such as stereo separation of stereo signals within the baseband signals.

Abstract: An analog to digital converter includes a first amplifier array connected to taps from a reference ladder, a second amplifier array, wherein each amplifier in the first amplifier array is connected to only two amplifiers of the second amplifier array, a third amplifier array, wherein each amplifier in the second amplifier array is connected to only two amplifiers of the third amplifier array, and an encoder connected to outputs of the third amplifier array that converts the outputs to an N-bit digital signal.

Abstract: A metal-insulator-metal (MIM) capacitor is made according to a copper dual-damascene process. A first copper or copper alloy metal layer if formed on a substrate. A portion of the first metal layer is utilized as the lower plate of the MIM capacitor. An etch stop dielectric layer is used during etching of subsequent layers. A portion of an etch stop layer is not removed and is utilized as the insulator for the MIM capacitor. A second copper or copper alloy metal layer is later formed on the substrate. A portion of the second metal layer is utilized as the upper plate of the MIM capacitor.

Abstract: An online trusted platform module (TPM) in communication with a security module that can be located elsewhere in the network in a server machine. In an embodiment, the online TPM is connected directly to a network interface card (NIC) that is also resident at the client. This allows the online TPM to communicate directly to the network, and therefore to the security module (without having to deal with the TCP/IP stack at the client machine in some circumstances, e.g., the boot process). In an embodiment, the communications channel between the online TPM and the security module is implemented using the transport layer security (TLS) protocol. A secure boot process is performed in advance of security processing. Typical security processing includes receipt, by the online TPM, of one or more commands from an application. The online TPM then proxies out the commands to the security module.

Abstract: A security architecture in which a security module is integrated in a client machine, wherein the client machine includes a local host that is untrusted. The security module performs encryption and decryption algorithms, authentication, and public key processing. The security module also includes separate key caches for key encryption keys and application keys. A security module can also interface a cryptographic accelerator through an application key cache. The security module can authorize a public key and an associated key server. That public key can subsequently be used to authorize additional key servers. Any of the authorized key servers can use their public keys to authorize the public keys of additional key servers. Secure authenticated communications can then transpire between the client and any of these key servers. Such a connection is created by a secure handshake process that takes place between the client and the key server.

Abstract: A communication system includes a link module having a first serial interface for interfacing to a serial link. The link module also including a second serial interface. The system also includes a Media Access Control (MAC) module including a parallel interface. The system also includes a converter module, coupled between the parallel interface and the second serial interface, configured to convert symbols, transferred between the parallel interface and the second serial interface, between a parallel format at the parallel interface and a serial format at the serial interface.