Abstract: An apparatus may include at least a first transistor, a second transistor, and a circuit. The first transistor has a first control terminal coupled to receive a first dynamic data signal, and is coupled to a first node. The first transistor drives a first state on the first node responsive to an assertion of the first dynamic data signal. The second transistor is coupled to the first node and has a second control terminal. The second transistor is drives a second state on the first node responsive to a signal on the second control terminal. The circuit is coupled to generate the signal on the second control terminal and is coupled to receive a second dynamic data signal. The second dynamic data signal is a complement of the first dynamic data signal, wherein the circuit is activates the second transistor responsive to an assertion of the second dynamic data signal.

Abstract: A media access controller, which includes an output buffer and a clock controller, is provided. The output buffer includes a first and second clock input. The first clock is configured to control data input into the buffer and the second clock is configured to control data output from the buffer. The clock controller is coupled to the output buffer and configured to regulate a first clock signal input into the first clock input to control the data input into the buffer.

Abstract: A network device includes at least one first network port, at least one second network port, a MUX unit and a switching unit. The MUX unit is connected to the at least one first network port. The MUX unit includes a trunk circuit and an output. The trunk circuit is configured to aggregate data packets received at the at least one first port into a trunk group and to output trunked data packets to the output. The switching unit is connected to the output of the MUX unit and to the at least one second network port. The switching unit is configured to switch the trunked data packets to the at least one second network port.

Abstract: A network device includes at least a plurality of ports, a memory pool, and a service differentiation module. The plurality of ports is configured to send and receive data packets, and at least one port of the plurality of ports is connected to at least one network entity. The memory pool is configured to store the data packets. The service differentiation module is coupled with the memory pool, and is configured to regulate storage of the data packets in the memory pool based upon a comparison of terms negotiated between at least two network entities.

Abstract: A ROM or other memory may include two or more partitions and a precharge circuit. Each of the partitions may be coupled to separate sets of output conductors, to which the precharge circuit may be coupled. The precharge circuit may precharge the conductors of the partition to be read, while not precharging the other conductors. In one embodiment, the precharge may be to a voltage representing a binary value. In one implementation, the non-precharged conductors may be held to a predetermined voltage different from the voltage to which the precharged conductors are precharged. The predetermined voltage may represent the opposite binary value to the binary value represented by the precharge voltage. The ROM may also include an output circuit which may, in certain embodiments, comprise a logic circuit which logically combines the signals on respective conductors from each partition to provide output signals from the ROM.

Abstract: A circuit for applying power to mixed mode integrated circuits in a predefined sequence. The circuit includes a first circuit powered by a first voltage and a second circuit powered by a second voltage that is less than the first voltage and having the second voltage coupled to the first circuit. The circuit for applying power to mixed mode integrated circuits includes a modified I/O cell of the second circuit. The modified I/O cell has a driver transistor including a back gate terminal, a gate terminal that is driven by the second circuit, a drain terminal that is coupled to a first circuit signal, and a source terminal that is coupled to the second voltage. The circuit for applying power to mixed mode integrated circuits further includes a controller circuit coupled to the first voltage and the second voltage supplied as controller circuit inputs. The controller circuit has a plurality of controller circuit outputs.

Abstract: Provided is a system for implementing gain control in an amplification module comprising a first stage amplifier having a number of first stage input and output ports. The first stage amplifier is configured to provide first stage amplification to a received input signal and produce from the amplified input signal a number of output signals. Also included are a number of second stage amplifiers, each having second stage input and output ports, the second stage input ports being respectively coupled to the first stage output ports and being configured to receive the number of output signals. A gain control device is coupled to at least one from the group including the first stage input ports, the first stage output ports, and the second stage output ports. The gain control device is also configured to control a gain of at least one of the first stage amplifier and one or more of the number of second stage amplifiers.

Abstract: Methods and systems for maintaining desired circuit and/or signal characteristics, such as impedance matching characteristics and rise and fall time characteristics, over a range of PVT variations. In an embodiment, a PVT compensating circuit senses one or more circuit and/or signal characteristics at an output pad or terminal. When the one or more circuit and/or signal characteristics are affected by PVT variations in the IC and/or load, the PVT compensating circuit controls a variable output drive to maintain the one or more circuit and/or signal characteristics within a desired or predetermined range. The PVT compensating circuit is designed to compensate over a range of PVT variations. In an embodiment, the PVT compensating circuit senses a rate of voltage change over time (i.e., dV/dt), of an output signal at the output terminal. During state transitions of the output signal, the output signal is adjusted as needed to maintain a desired, or predetermined, rate of voltage change.

Abstract: Improved carrier recovery, symbol timing, and carrier phase tracking systems and methods suitable for use in connection with a dual-mode QAM/VSB receiver system are disclosed. Carrier and phase recovery systems operate on complex signals representing symbols having the same time stamp for each phase error term. in-phase signals are sampled twice a symbol at the in-phase symbol sampling time and at the quadrature-phase symbol sampling time. The signals are de-multiplexed to generate I and XI data streams, where I represents the in-phase sampling time signals and XI represents mid-symbol point sample times. A similar procedure is carrier out on quadrature-phase signals. When the in-phase signal is de-multiplexed to generate a symbol I, the quadrature-phase signal is de-multiplexed to generate its mid-symbol point XQ. Both I and Q are decoded in a decision device to define a symbol error term, which is combined with the opposite mid-symbol signal to define a phase error term PI and PQ for each rail.

Abstract: Methods and apparatus for improving the current matching within current mirror circuits in applications such as low voltage integrated circuits. Embodiments of the present invention attempt to maintain the proper current ratio between reference and output supplies by adjusting the reference output of the current mirror. An existing reference voltage on the output side of the mirror can be used or a reference voltage can be created to be used for the voltage regulation of the reference side of the current mirror.

Abstract: A node comprises one or more resources and a register programmable with an indication during use. The one or more resources are addressed with addresses within a local region of an address space. The indication identifies a second region of the address space that is aliased to the local region, and other nodes address the one or more resources using addresses in the second region.

Abstract: A linearized oscillation synthesizer includes a phase and frequency detection module, charge pump circuit, low pass filter, voltage control oscillator, and a feedback module. The phase and frequency detection module is operably coupled to produce a charge-up signal, a charge-down signal, and an off signal based on phase and/or frequency differences between a reference oscillation and a feedback oscillation. The reference oscillation is generated by a clock source such as a crystal oscillator while the divider module generates the feedback oscillation by dividing the output oscillation by a divider value. The charge pump circuit produces a positive current in response to the charge-up signal, a negative current in response to the charge-down signal and also produces a non-zero offset current. The non-zero offset current shifts the steady state operating condition, and other operating conditions, of the charge pump into a linear region of charge pump performance curve.

Abstract: Methods and apparatus are provided for an entity such as a CPU to efficiently call a cryptography accelerator to perform cryptographic operations. A function call causes the cryptography accelerator to execute multiple cryptographic operations in a manner tailored for specific processing steps, such as steps during a handshake phase of a secured session. The techniques provide efficient use of hardware processing resources, data interfaces, and memory interfaces.

Abstract: A linearized oscillation synthesizer includes a phase and frequency detection module, charge pump circuit, low pass filter, voltage control oscillator, and a feedback module. The phase and frequency detection module is operably coupled to produce a charge-up signal, a charge-down signal, and an off signal based on phase and/or frequency differences between a reference oscillation and a feedback oscillation. The reference oscillation is generated by a clock source such as a crystal oscillator while the divider module generates the feedback oscillation by dividing the output oscillation by a divider value. The charge pump circuit produces a positive current in response to the charge-up signal, a negative current in response to the charge-down signal and also produces a non-zero offset current. The non-zero offset current shifts the steady state operating condition, and other operating conditions, of the charge pump into a linear region of charge pump performance curve.

Abstract: An IQ receiver includes an estimator/compensator module to determine and correct IQ mismatch errors between the I and Q channels of the IQ receiver. The estimator module determines a phase compensation factor C1 and an amplitude compensation factor C2 based on a calibration signal that is injected into the analog front-end of the IQ receiver. A compensator module applies the phase correction factor C1 and the amplitude correction factor C2 to the baseband output of the Q channel in order to reduce any phase or amplitude errors between the I and Q channels. The estimator module and the compensator module can be efficiently implemented in a digital state machine, or processor, including a digital signal processor.

Abstract: Methods and apparatus are provided for performing authentication and decryption operations. A record including multiple encrypted blocks is received. An encrypted block in the record is extracted and decrypted first in order to obtain context information for performing authentication operations. Each remaining block is then decrypted and authenticated by using the available context information. Authentication operations can be performed without having to wait for the decryption of all of the blocks in the record.

Abstract: A reference ladder is configured to have improved feedback stability. The reference ladder includes a resistor ladder having a plurality of taps that produce a plurality of reference voltages. The resistor ladder is driven by a first current source at a first tap of the plurality of taps and by a second current source at a second tap of the plurality of taps. A first feedback network senses a voltage at the first tap and controls the first current source based on the first sensed voltage. A second feedback network senses a voltage at the second tap and controls the second current source based on the second sensed voltage. The first and second taps each operate as both a force tap and a sense tap of the resistor ladder. Differential input stages that are connected to the plurality of taps are at least partially isolated from the feedback networks by converging the force and sense taps, thereby improving the stability of the feedback networks.

Abstract: Clock signals and digital data signals at a variable frequency are introduced to the input of a FIFO and are passed from the FIFO at a second (or intermediate) frequency controlled by a numerically controlled oscillator. To regulate the frequency of the signals from the numerically controlled oscillator, the phases of the clock signals at the variable frequency are compared in a phase detector with the phases of the signals from the numerically controlled oscillator to generate an error signal. The error signals and the signals at a fixed sampling frequency higher than the intermediate frequency regulate the frequency of the signals from the numerically controlled oscillator and thus the frequency of the digital data signals from the FIFO. The digital data signals from the FIFO are converted to a pair of signals at the second frequency.

Abstract: An analog to digital converter includes a first amplifier array connected to taps from a reference ladder, a second amplifier array, wherein each amplifier in the first amplifier array is connected to only two amplifiers of the second amplifier array, a third amplifier array, wherein each amplifier in the second amplifier array is connected to only two amplifiers of the third amplifier array, and an encoder connected to outputs of the third amplifier array that converts the outputs to an N-bit digital signal.

Abstract: A communication network having at least one access point supports wireless communication among a plurality of wireless roaming devices via a first and a second wireless channel. The access point comprises a first and a second transceiver. The first and second transceivers operate on the first and second wireless channels, respectively. Each of the plurality of wireless roaming devices are capable of communicating on the first and second wireless channel. In one embodiment, the first wireless channel is used to exchange data, while the second channel is used to manage such exchanges as well as access to the first channel. In an alternate embodiment, both channels are used to support communication flow, however the first channel supports a protocol that is more deterministic than that of the second channel. Allocation of ones of the plurality of wireless roaming devices from one channel to the next may occur per direction from the access point.