Abstract: A distributed CMTS in a hybrid fiber/coaxial (HFC) plant. The distributed CMTS comprises at least one network layer, at least one media access control layer, and one or more physical layers. The at least one network layer, at least one media access control layer and one or more physical layers each function as separate modules, enabling them to be in separate locations, yet physically connected, throughout the HFC plant.

Abstract: A miniMAC implementation of a distributed CMTS in a hybrid fiber/coaxial (HFC) plant. The distributed CMTS comprises at least one network layer, at least one media access layer, and one or more physical layers. The at least one media access layer includes one or more miniMAC layers. The one or more miniMAC layers are remotely located from a remaining part of the at least one media access layer. The at least one network layer, the remaining part of the at least one media access layer, the one or more miniMAC layers, and the one or more physical layers each function as separate modules, enabling each layer to be in separate component locations of the HFC plant, yet having the at least one network layer connected to the remaining part of the at least one media access layer, the at least one media access layer connected to each of the one or more miniMAC layers, and each of the one or more physical layers connected to each of the one or more miniMAC layers.

Abstract: A distributed cable modem termination system (CMTS) in a hybrid fiber/coaxial (HFC) plant. The distributed CMTS comprises a network layer, at least one media access control layer, and at least one physical layer. The media access control layer implements a media access control chip. The media access control chip interfaces with the physical layer to provide timing to maintain components within the physical layer. The network layer, media access control layer, and physical layer each function as separate modules. The media access control chip provides the packet level media access control functions, and thus, does not require packet level media access control functions to be implemented in the same physical location. The media access control chip also provides a timing offset feature for handling time delays between the media access layer and the physical layer.

Abstract: Limit-cycle oscillations are caused by the compounding of quantization errors that occurs when previous digital filter outputs are used as inputs to the digital filter for the current operation. Where a signal in a digital waveform has become a constant common value applied to the input of the digital filter (indicative that the digital waveform has suspended conveyance of data), limit-cycle oscillations often appear as “random” outputs, with values different from the common value, that occur long after the signal in the digital waveform has become the constant common value. Limit-cycle oscillations are manifested as noise in the filtered digital waveform. Such noise hampers the ability of the system to extract the signal from the filtered digital waveform. The present invention identifies the occurrence of a limit-cycle oscillation as an output different from the common value. The identified limit-cycle oscillation is set equal to the common value.

Abstract: A distributed cable modem termination system (CMTS) in a hybrid fiber/coaxial (HFC) plant. The distributed CMTS comprises a network layer, at least one media access control layer, and at least one physical layer. The media access control layer implements a media access control chip. The media access control chip interfaces with the physical layer to provide timing to maintain components within the physical layer. At least one physical layer is connected to a respective at least one media access control layer. The network layer, media access control layer, and physical layer each function as separate modules. The media access control chip does not require packet level media access control functions to be implemented in the same physical location. This enables the network layer to be in a separate component location of the HFC plant from the at least one media access control layer and the at least one physical layer, yet physically connected throughout the HFC plant.

Abstract: In a latch circuit having a bistable pair of cross connected transistors of a first polarity and a third transistor of a second polarity, a current signal greater than a bias current is received at a latch circuit port, amplified with the third transistor, and applied to the latch circuit port. This decreases the time in which the latch circuit port receiving the current signal greater than the bias current reaches a steady state voltage.

Abstract: An analog to digital converter includes an array of differential input amplifiers. Each amplifier inputs an input voltage and a corresponding voltage reference, and outputs a differential signal representing a comparison of the input voltage and the corresponding voltage reference. A plurality of latches stores the differential signal from each of the differential input amplifiers. A decoder converts the stored differential signals to N-bit digital output. A first interface amplifier is connected to a first edge amplifier of the array through a first cross point. A second interface amplifier is connected to a second edge amplifier of the array through a second cross point. The first interface amplifier and the second interface amplifier are connected to each other through a third cross point.

Abstract: A balancing/unbalancing (balun) structure includes a microstrip line printed circuit board (PCB). Two input ports are coupled to a differential signal. An isolated port is connected to ground through a resistance. An output port is coupled to a single-ended signal corresponding to the differential signal. A plurality of traces on the PCB connect the two input ports, the load connection port and the output port, wherein distance between adjacent traces is approximately twice PCB thickness.

Abstract: A system reduces unwanted oscillations in a multiple gigabit per second, high gain amplifier portion. The system includes a power source portion having a plurality of power sources and a bias current portion having a plurality of bias current devices. The system also includes an amplification portion having a plurality of amplifiers. A first group of the plurality of amplifiers is coupled to the power source portion and the bias current portion, such that feedback voltage is substantially eliminated to substantially eliminate oscillations in the amplification portion.

Abstract: A balancing/unbalancing (balun) structure for operating at frequency f1 includes a microstrip printed circuit board (PCB). A balun on the PCB includes two input ports are coupled to a differential signal. An isolated port is connected to ground through a matched resistance. An output port is coupled to a single-ended signal corresponding to the differential signal. A plurality of traces on the PCB connect the two input ports, the load connection port and a tap point to the output port. A f2 rejection filter on the PCB is wrapped around the balun and includes a first folded element with a transmission length of &lgr;2/4 and connected to the output port. A second folded element has a transmission length of &lgr;2/4 and connected to the tap point. A third folded element connects the tap point to the output port and has a transmission length of &lgr;2/4.

Abstract: A shared buffer packet switching device is provided for receiving data packets via associated ones of a plurality of receive ports, and for transmitting data packets via associated selected ones of a plurality of transmit port.

Abstract: A graphics integrated circuit chip is used in a set-top box for controlling a television display. The graphics chip processes analog video input, digital video input, and graphics input. The chip blends graphics and video information by various graphics windows using alpha values for the windows, alpha values per pixel, or both. The chip calculates a composite alpha value based on the window's alpha values and the alpha values per pixel. Blended graphics and video may then be composited using the composite alpha value.

Abstract: An arbiter circuit is provided for resolving a plurality of N request signals received from a plurality of agents requesting access to a resource.

Abstract: An anti-fuse device includes a substrate and laterally spaced source and drain regions formed in the substrate. A channel is formed between the source and drain regions. A gate and gate oxide are formed on the channel and lightly doped source and drain extension regions are formed in the channel. The lightly doped source and drain regions extend across the channel from the source and the drain regions, respectively, occupying a substantial portion of the channel. Programming of the anti-fuse is performed by application of power to the gate and at least one of the source region and the drain region to break-down the gate oxide, which minimizes resistance between the gate and the channel.

Abstract: Digital data signals at a variable input frequency are converted by a numerically controlled oscillator and an interpolator to a signal at a fixed output sampling frequency. The conversion of the variable input frequency to the fixed output sampling frequency may be by a factor other than an integer. The interpolated digital data signals at the fixed output sampling frequency are then modulated into a pair of trigonometric signals at a programmable carrier frequency, one signal having a cosine function and the other signal having a sine function. The modulated signals at the fixed output sampling frequency are then combined to create a modulated signal at a carrier frequency determined by the frequency of the sine and cosine signals. The modulated signal is sampled at the fixed output sampling frequency and converted to a corresponding analog signal using a digital-to-analog converter.

Abstract: A Finite Impulse Response (FIR) filter is implemented in software on a general purpose processor in a manner which reduces the number of memory accesses as compared to conventional methods.

Abstract: A reduced state maximum likelihood sequence estimator allows the use of improved equalization techniques that provides greatly improved performance for channels with severe attenuation and spectral nulls. The reduced state maximum likelihood sequence estimator retains kn states of a total number of K states, kn<K, with each retained state having an associated state metric. (J)(kn) new states are determined based on kn previous states and a most recently received sample, using J transitions, J being a less than L, where L is a size of a symbol alphabet. (J)(kn) new state metrics are determined which are respectively associated with each new state. The new state metrics are compared to a threshold and those states whose metric does not exceed the threshold are retained. The reduced complexity of the MLSE allows for the use of partial response equalizers, e.g., a partial response class V (PRV) equalizer.

Abstract: A communications network switch includes a plurality of network ports for transmitting and receiving packets to and from network nodes via network links, each of the packets having a destination address and a source address, the switch being operative to communicate with at least one trunking network device via at least one trunk formed by a plurality of aggregated network links. The communications network switch provides a method and apparatus for balancing the loading of aggregated network links of the trunk, thereby increasing the data transmission rate through the trunk.

Abstract: A system for receiving signals (e.g., optical signals) includes an input device, an amplification device, and a feedback device. The amplification device receives a signal from the input device and includes a transimpedance portion. The transimpedance portion includes a first section having a plurality of elements (e.g., resistors and transistors) and a second section having a plurality of elements (e.g., resistors and transistors). One or more of the elements (e.g. transistors or resistors) in the first and second sections are mismatched to introduce a systematic offset in the transimpedance stage, to make the net input referred offset of the amplification device unidirectional. The feedback device (e.g. an integrator) is coupled to an output of the amplification device and an input of the transimpedance portion to provide a unidirectional offset correction to the amplification device for reduced noise enhancement.

Abstract: Multi-concentric pad (MCP) arrangements provide for increased pad densities on integrated circuits. The multi-concentric pad (MCP) configuration includes a first set of input output (IO) pads and a second set of IO pads, both disposed on an integrated circuit die. Each IO pad in said first set and said second set of IO pads includes a bond pad for receiving a bond wire connection, and an IO circuit coupled to the bond pad. The IO circuits provide an interface between a signal received at the corresponding bond pad and a core circuit disposed on said IC die. The first set of IO pads are arranged closer to the perimeter of the IC die than the second set of IO pads. Furthermore, the second set of IO pads are arranged so that each IO circuit in the second set of IO pads is closer to the center of the IC die than a corresponding IO circuit in the first set of IO pads.