Abstract: Various systems and methods providing clock delay compensation for circuits such as a multi-pair gigabit Ethernet transceiver are disclosed. In an analog implementation a buffer with an adjustable delay may be used to minimize the delay mismatch between clock trees. The delay of the adjustable-delay buffer is controlled by bias voltages that determine the charging and discharging current to the adjustable buffer. A phase detector circuit is used to compare the clock phases for rising and falling edges, and to adjust the bias voltages that control these edges. In a digital implementation a selector switch, responsive to a phase detector, may be used to route clock signals through circuit elements to delay clock signals.

Abstract: Methods and systems for sensing load conditions and for adjusting output current drive according to the sensed load conditions to maintain one or more signal characteristics within a desired range. Load conditions are sensed by monitoring one or more signal characteristics that are affected by load conditions, such as voltage changes with respect to time. Output current drive is then adjusted, as needed, to maintain the one or more desired signal characteristics. Depending upon the load conditions, a supplemental current is generated and/or adjusted and added to the output signal to maintain the desired signal characteristics within a desired range.

Abstract: A buffer architecture and latency reduction mechanism for buffering uncompressed/compressed information. This combination provides for a proficient division of the encoding task and quicker through-put time. The invention teaches a single chip digital signal processing device for real time video/audio compression comprising a plurality of processors, including a video input processor, a motion estimation processor, a digital signal processor, and a bitstream processor, wherein processing and transfer of the signals within the device is done in a macroblock-by-macroblock manner. The device can include a multiplexing processor that is comprised of a storage unit which buffers a compressed video bitstream and a processor which retrieves the compressed video bitstream from the storage unit and produces a multiplexed data stream whereby the compressed video bitstream is processed in a pipeline manner.

Abstract: A receiver includes a filter for filtering a received signal to produce a filtered signal. A converter converts the filtered signal to a baseband signal that is substantially free of an initial frequency offset and inter-symbol interference (ISI), responsive to a frequency-offset estimate and a restorative signal that compensates for the ISI. A detector detects symbols in the baseband signal to produce a decision signal. A restorative signal generator generates, from the decision signal, the restorative signal responsive to the frequency-offset estimate, such that the restorative signal compensates for the ISI.

Abstract: A power efficient and reduced electromagnetic interference (EMI) emissions transmitter for unshielded twisted pair (UTP) data communication applications. Transmit data is processed by a digital filter. The digital filter output data is converted to a current-mode analog waveform by a digital-to-analog converter (DAC). The digital filter is integrated with the DAC binary decoder in a memory device such as a ROM with time multiplexed output. DAC line driver cells are adaptively configurable to operate in either a class-A or a class-B mode depending on the desired operational modality. A discrete-time analog filter is integrated with the DAC line driver to provide additional EMI emissions suppression. An adaptive electronic transmission signal cancellation circuit separates transmit data from receive data in a bidirectional communication system operating in full duplex mode.

Abstract: A system is provided for activating gain stages in an amplification module. The system includes an amplification module including a first group of amplifiers. Inverting output ports of each of the first group of amplifiers are coupled to a module inverting output terminal, and non-inverting output ports are coupled to a module non-inverting output terminal. A divider network is provided and is coupled to the input ports of the first group of amplifiers. A second group of amplifiers is also provided. Each amplifier of the second group corresponds to one of the amplifiers in the first group, has an inverting input port coupled to the second module inverting input terminal and to output ports of the divider network, and a non-inverting input port coupled to the second non-inverting input terminal.

Abstract: An adaptive retry mechanism may record latencies of recent transactions (e.g. the first data transfer latency), and may select a retry latency from two or more retry latencies. The retry latency may be used for a transaction, and may specify a point in time during the transaction at which the transaction is retried if the first data transfer has not yet occurred. In one implementation, the set of retry latencies includes a minimum retry latency, a nominal retry latency, and a maximum retry latency. The nominal retry latency may be set slightly greater than the expected latency of transactions in the system. The minimum retry latency may be less than the nominal retry latency and the maximum retry latency may be greater than the nominal retry latency. If latencies greater than the nominal retry latency but less than the maximum retry latency are being experienced, the maximum retry latency may be selected.

Abstract: A method and apparatus for using a general purpose input-output (GPIO) interface to test a user input device such as a wireless keyboard or mouse. Operation of the key-scan logic can be tested by the GPIO interface by temporarily disconnecting the outputs of the various rows and columns and substituting signals generated by a test algorithm into the input terminals of the key-scan logic. The test signal is processed by the key scan circuitry and a key-scan output signal is generated. This key-scan output signal is then compared to a known reference output signal to determine if the key-scan logic and associated circuitry is operating properly. In another embodiment, the GPIO testing system operates in conjunction with other user devices such as a computer mouse/scrolling device.

Abstract: Methods and systems for modifying DOCSIS-based transmission paths for communication in higher frequency and/or wireless environments, such as wireless terrestrial communication systems and satellite communication systems. An inner turbo-code is combined with a DOCSIS based Reed-Solomon (“RS”) forward error correction (“FEC”) coding scheme, to produce a concatenated turbo-RS code (other FEC codes can be utilized). In phase and quadrature phase (“I-Q”) processing is utilized to enable relatively low cost up-converter implementations. The I-Q processing is preferably performed at baseband, essentially pre-compensating for analog variations in the transmit path. Power amplifier on/off control capable of controlling on/off RF power control of remote transmitters is modulated on a transmit cable to reduce the need for a separate cable.

Abstract: Methods and apparatuses for spectrally shaping mismatch errors in a multi-bit digital to analog converter (DAC). In an embodiment, the multi-bit DAC is constructed from K separate multi-element sub-DACs, where K and the number of elements in each sub-DAC are each preferably greater than two. A received digital input code is split into a set of K sub-codes corresponding to the digital input code. The set of K sub-codes can have one of at least N different sub-code orders that specify an order of each of the K sub-codes with respect to one another, where N>2. A sum of the K sub-codes equals the digital input code. One of the at least N different sub-code orders is selected using a shuffling algorithm. Then, each sub-code in the set of K sub-codes is output in accordance with the selected sub-code order.

Abstract: Driver circuits of the present invention provide current to drive laser diodes. The output current of the driver circuit includes a data signal and a low frequency tone signal. The low frequency tone signal is within the bandwidth of a power control feedback loop. The tone signal introduces low frequency noise into the output signal of the driver circuit. The low frequency noise causes jitter at the zero crossing points of the driver circuit output signal. A laser driver circuit of the present invention provides a compensation current to a laser diode. The compensation current is out of phase with the tone signal. The compensation current eliminates the low frequency noise in the output signal of the laser driver circuit.

Abstract: An anti-fuse device includes a substrate and laterally spaced source and drain regions formed in the substrate. A channel is formed between the source and drain regions. A gate and gate oxide are formed on the channel and lightly doped source and drain extension regions are formed in the channel. The lightly doped source and drain regions extend across the channel from the source and the drain regions, respectively, occupying a substantial portion of the channel. Programming of the anti-fuse is performed by application of power to the gate and at least one of the source region and the drain region to break-down the gate oxide, which minimizes resistance between the gate and the channel.

Abstract: A differential driver includes a switching module and first and second voltage controlled voltage sources. The switching module has a plurality of switches each controlled by an input signal, a first voltage input and a second voltage input, and a signal output. The first voltage controlled voltage source is connected to the first voltage input. The first voltage controlled voltage source has a low impedance. The second voltage controlled voltage source is connected to the second voltage input. The second voltage controlled voltage source also has a low impedance. The switching circuit outputs an output signal having an output voltage and current controlled by the first and second voltage controlled voltage sources. The output signal is based upon the input signal.

Abstract: A first dynamic logic circuit has an output node on which a scan value is provided during scan. One of one or more second dynamic logic circuits has an input coupled to the output node of the first dynamic logic circuit, and an output of the second dynamic logic circuits is sampled in response to the scan value during scan. In one embodiment, clock generation circuitry may be included which generates a first clock, a second clock, and a third clock. At least one evaluate pulse on the first clock prior is generated prior to sampling the output of the second dynamic logic circuits, the first clock controlling at least the evaluation of the second dynamic logic circuits. The second and third clocks are generated to isolate the output node from inputs to the first dynamic logic circuit responsive to the scan mode signal indicating that scan is active.

Abstract: Method and apparatus for determining the stopping point of an iterative decoding process. In one embodiment the estimated values of an iteration of an iterative decoder are provided to a signature circuit. If the signature does not differ from the previous signature developed from a prior iteration, or the signature developed from an iteration prior to the previous iteration, the decoding stops. The variance may also be tested and compared to a threshold as a criteria to stop the iterative decoding.

Abstract: A high output power radio frequency integrated circuit includes an up conversion module, a plurality of drivers and a plurality of integrated circuit pads. The up conversion module is operably coupled to convert a low intermediate frequency (IF) signal into a radio frequency (RF) signal. The plurality of drivers are operably coupled to receive the RF signal and to produce separate RF drive signals therefrom. The plurality of integrated circuit pads are coupled to the plurality of drivers to provide the separate RF drive signals to external components of the RFIC.

Abstract: A physical layer device (PLD), comprising: a first serializer-deserializer (SERDES) device having a first parallel port; a second SERDES device having a second parallel port; a third SERDES device having a third parallel port; and a path selector being selectively configurable to provide either (i) a first signal path between the first and second parallel ports, or (ii) a second signal path between the first and third parallel ports.

Abstract: A method and apparatus for obtaining a channel estimate and a baud frequency offset estimate for a communications channel in a communications system. The communications system has a transmitter for transmitting to a receiver over the communications channel signals representing data appended to a preamble signal. The preamble signal is provided as a periodic plurality of preamble sequences, each preamble sequence being generated in accordance with: 1 1 32 ⁢ ∑ k = 0 15 ⁢   ⁢ b k ⁢ b mod ⁡ ( k + n , 16 ) * = { 1 , n = 0 0 , n ≠ 0 .

Abstract: A method of providing bias voltages for input output connections on low voltage integrated circuits. As integrated circuit voltages drop generally so does the external voltages that those circuits can handle. By placing input and output devices, in series, external voltages can be divided between the devices thereby reducing junction voltages seen by internal devices. By using external voltages as part of a biasing scheme for integrated circuit devices, stress created by the differential between external voltages and internal voltages can be minimized. Additionally device wells can be biased so that they are at a potential that is dependant on the external voltages seen by the low voltage integrated circuit.

Abstract: A method, apparatus and computer program product for generating and processing upstream channel descriptor (UCD) messages in a DOCSIS-based broadband communications system, such as a DOCSIS-based two-way satellite communications system, is provided. A satellite modem termination system (SMTS) generates a UCD message that includes one or more standard parameters pertaining to an upstream channel of the two-way satellite communications system, wherein the one or more standard parameters are defined in accordance with the DOCSIS protocol, and one or more satellite application-specific parameters pertaining to the upstream channel, wherein the one or more satellite application specific parameters are not provided for by the DOCSIS protocol. The UCD message is transmitted to a satellite modem that extracts both the standard and satellite application-specific parameters for use in managing communication over the upstream channel.