Abstract: A method for reducing bit errors in an analog to digital converter having an array of comparators. The outputs of first and second comparators are received as in inputs to an Exclusive OR gate. The first and second comparators are separated in the array by a third comparator. The output of the Exclusive OR gate is used to determine if the third comparator is in a metastable condition. If the third comparator is in a metastable condition, the bias current of the latch circuit of the third comparator is increased to increase the rate at which the third comparator transitions to a steady state.

Abstract: A design of integrated circuit components to prevent accidental turn on when large input signals are accepted. With integrated circuits operated at lower power supply voltages, input signals having large peak values can tend to turn on devices within the integrated circuit erroneously. By placing amplifiers within the integrated circuits where input signals are received and removing the power of such amplifiers, accidental turn on can be minimized.

Abstract: An N-bit analog to digital converter includes a reference ladder connected to an input voltage at one end, and to ground at another end, an array of differential amplifiers whose differential inputs are connected to taps from the reference ladder, wherein each amplifier has a first differential input connected to the same tap as a neighboring amplifier, and a second differential input shifted by one tap from the neighboring amplifier, and an encoder that converts outputs of the array to an N-bit output.

Abstract: A periodic signal generation circuit includes a differential crystal oscillator suitable for integration on a semiconductor substrate. The oscillator utilizes an external crystal as a resonator. The circuit is designed such that differential sinusoidal signals are present on the resonator leads to provide superior noise rejection of interfering signals. Differential signal transmission is maintained throughout the oscillator to reject noise generated by other circuitry that may be present on the substrate. Noise radiated out from the oscillator through the power supply, substrate, bond wires and pads is reduced due to the generation of differential signals of controlled sinusoidal amplitude and low harmonic content. The oscillator produces low phase noise so that the oscillator may be used in applications, such as TV receivers, that are sensitive to distortion. The circuit is a square wave that has low jitter, thus reducing jitter produced in digital circuits that would utilize this square wave clock signal.

Abstract: A data transceiver module for digital data communications in a portable hand-held data terminal has multiple data spread spectrum modes which include direct sequence and frequency function modulation algorithms. The transceiver module has multiple user or program configurable data rates, modulation, channelization and process gain in order to maximize the performance of radio data transmissions and to maximize interference immunity. Various module housings, which may be PCMCIA type, are able to be mated with a suitably designed data terminal. Media access control protocols and interfaces of multiple nominal operational frequencies are utilized. Wireless access devices in a cell based network each consider a variety of factors when choosing one of a plurality of modes of wireless operation and associated operating parameters. Such selection defines a communication channel to support wireless data, message and communication exchanges.

Abstract: A memory-efficient convolutional interleaver/deinterleaver with a memory array, a write commutator, and a read commutator wherein the commutators perform their respective write and read operations relative to a preselected memory cell after a predetermined delay. The delay is chosen using a modulo-based technique, such that an efficient implementation of a Ramsey Type-II interleaver is realized.

Abstract: An extended range variable gain amplifier is described. The variable gain capability is achieved by replacing differential pair amplifiers having an input signal with less attenuation with one having an input signal that is more attenuated. This replacement continues until only ten differential pair amplifiers are remaining. At this point, if less gain is desired, differential pair amplifiers are turned off, but are not replaced. A minimum number of amplifiers will remain on.

Abstract: A cache is configured to select a cache block for eviction in response to detecting a cache miss. The cache transmits the address of the cache block as a write transaction on an interface to the cache, and the cache captures the address from the interface and reads the cache block from the cache memory in response to the address. The read may occur similar to other reads in the cache, detecting a hit in the cache (in the cache storage location from which the cache block is being evicted). The write transaction is initiated before the corresponding data is available for transfer, and the use of the bus bandwidth to initiate the transaction provides an open access time into the cache for reading the evicted cache block.

Abstract: Methods and circuitry for implementing high speed first-in first-out (FIFO) structures. In one embodiment, a FIFO is disclosed that allows the frequency of one clock, e.g., the write clock, to be different than (e.g., half) that of the other (read) clock. In another embodiment a FIFO is presented that can be set and/or reset asynchronously. Other embodiments are disclosed wherein the read and write pointers are effectively monitored to ensure proper timing relationship, to detect loss of clock as well as to detect other abnormal FIFO conditions.

Abstract: A network device for processing a packet can have at least one port within the network device configured to received or transmit a packet, and a storage unit configured to store a port bit map, wherein the port bit map corresponds to the at least one port. Furthermore, the network device for processing a packet can have a rules table configured to have at least one port match entry and at least one action corresponding to the at least one port match entry therein, and a control unit configured to compare the port bit map with the at least one port match entry, and to implement the at least one action when a first positive value results from comparing the port bit map with the port match entry.

Abstract: In one aspect, the invention describes a mechanism for refreshing multiple memory words (rows) per refresh cycle, the number of simultaneously refreshed rows being programmable by a small number of inputs. In another aspect, the invention discloses a mechanism for refreshing all banks or a programmable number of banks simultaneously in a multi-bank memory. In yet another aspect, the present invention describes a mechanism for refreshing a programmable multiple memory rows and a programmable multiple banks simultaneously.

Abstract: A method is used to determine information about a communication channel using an adaptive filter coupled to the channel. The adaptive filter includes adaptive filter coefficients. The filter coefficients are compared to filter coefficient thresholds. A determination is made whether one of a communication link and a channel fault exists. If a channel fault exists, a determination is made whether, i) a cable open condition exists in the channel, and ii) a cable short condition exists in the channel. An indication is made whether the channel is one of linked, open, and shorted.

Abstract: A differential latch includes a sample transistor section, a hold transistor section, a 1st gating circuit and a 2nd gating circuit. The sample transistor section is operably coupled to sample, when coupled to a supply voltage (e.g., VDD and VSS) a differential input signal. The hold transistor section is operably coupled to latch, when coupled to the supply voltage, the sampled differential input to produce a latched differential signal. The 1st gating circuit is operable to couple the sampled transistor section to the supply voltage in accordance with a 1st clocking logic operation and a 2nd clocking logic operation. The 2nd gating circuit is operable to couple the hold transistor section to the supply voltage in accordance with a 3rd clocking logic operation and a 4th clocking logic operation.

Abstract: A communications system, having a combination Reed-Solomon encoder and a Turbo-Code encoder Data frame configuration which may be changed to accommodate embedded submarkers of known value are embedded in with the data order to aid synchronization in the receiver system, by providing strings of known symbols. The string of known symbols may be the same as the symbols within a training header that appears at the beginning of a data frame. Frame parameters may be tailored to individual users and may be controlled by information pertaining to receivers, such as bit error rate, of the receiver. Additional headers may be interspersed within the data in order to assist in receiver synchronization. Frames of data may be acquired quickly by a receiver by having a string of symbols representing the phase offset between successive header symbols in the header training sequence in order to determine the carrier offset.

Abstract: The present invention relates to a high voltage switch used with a one-time programmable memory device and a method of setting a state of a one-time programmable memory device using such a high voltage switch. The memory device includes a plurality of one time programmable memory cells arranged in an array and adapted to be programmed using a high voltage, wherein each of the memory cells includes at least one storage element and two gated fuses connected to the storage element. A high voltage switch is connected to at least one of the memory cells and is adapted to switch in a high voltage.

Abstract: Various systems and methods providing signal delay compensation for circuits such as a multi-pair gigabit Ethernet transceiver are disclosed. In an analog implementation a buffer with an adjustable delay may be used to minimize the delay mismatch between clock trees. The delay of the adjustable-delay buffer is controlled by bias voltages that determine the charging and discharging current to the adjustable buffer. A phase detector circuit is used to compare the clock phases for rising and falling edges, and to adjust the bias voltages that control these edges. In a digital implementation a selector switch, responsive to a phase detector, may be used to route clock signals through circuit elements to delay clock signals.

Abstract: A system for transmitting subchannel data over the same media as high speed data, especially DC balanced high speed data. A digital transmitter receives subchannel data and modulates it onto a subchannel carrier as the host signal in the preferred embodiment using frequency shift keying. The FSK subchannel carrier is added by superposition to the high speed data signal. At the receiver, a low pass filter filters out the subchannel carrier frequency components which are then amplified and subjected to a two-pole anti-aliasing filter to remove the third and fifth harmonics. Analog-to-digital conversion is followed by a digital mix down to remove the subchannel carrier component using a local oscillator at the subchannel carrier frequency. An FIR low pass filter having a triangular time domain response performs anti-aliasing and leaves as an output only frequency components at the positive and negative deviation frequency for Mark and Space.

Abstract: A radio receiver includes a power control module for selectively powering down and powering up radio receiver elements in between known communication periods according to one aspect of the present invention. According to a second aspect of the invention, the radio receiver operates in a low power mode of operation and periodically “sniffs” to determine whether an access point has messages or communication signals to transmit to it.

Abstract: A bit stream multiplexer includes an input ordering block, a plurality of multiplexers, an output ordering block, and a loop back circuitry. A bit stream demultiplexer includes an input ordering block, a plurality of demultiplexers, and an output ordering block. During testing, the transmit multiplexing integrated circuit and the receive demultiplexing integrated circuit are coupled into a circuit tester. Then, a plurality of input lines of the transmit multiplexing integrated circuit are coupled to a plurality of output data lines of the circuit tester. A loop back output of the transmit multiplexing integrated circuit is then coupled to a loop back input of the receive demultiplexing integrated circuit. A plurality of output lines of the receive demultiplexing integrated circuit are coupled to a plurality of input data lines of the circuit tester.

Abstract: Methods and apparatus are provided for using explicit initialization vectors in both encryption and decryption processing. In one example, a sender generates an initialization vector, identifies cryptographic keys, encrypts data using the initialization vectors and the cryptographic keys, and transmits the encrypted data in a packet along with the initialization vector. A receiver identifies cryptographic keys, extracts the initialization vector from the received packet, and decrypts the encrypted data using the cryptographic keys and the initialization vector extracted from the received packet.