Abstract: A method of providing bias voltages for input output connections on low voltage integrated circuits. As integrated circuit voltages drop generally so does the external voltages that those circuits can handle. By placing input and output devices, in series, external voltages can be divided between the devices thereby reducing junction voltages seen by internal devices. By using external voltages as part of a biasing scheme for integrated circuit devices, stress created by the differential between external voltages and internal voltages can be minimized. Additionally device wells can be biased so that they are at a potential that is dependant on the external voltages seen by the low voltage integrated circuit.

Abstract: A graphics integrated circuit chip is used in a set-top box for controlling a television display. The graphics chip processes analog video input, digital video input, a graphics input and an audio input simultaneously. The chip processes graphics images organized as windows. The chip obtains data that describes the windows, sorts the data according to the depth of the window on the display, transfers graphics images from memory, and blends the graphics images using alpha values associated with the graphics images.

Abstract: A transition delay matching circuit in which the transition delay of the divided clock signal is substantially the same as the transition delay of the reference clock signal. The transition delay of the divided clock signal is adjusted by reducing the steady state amplitude of the divided clock signal. Apparatuses and methods for matching the transition delays of the divided clock signal and the reference clock signal are disclosed.

Abstract: An integrated communications system. Comprising a substrate having a receiver disposed on the substrate for converting a received signal to an IF signal. Coupled to a VGA for low voltage applications and coupled to the receiver for processing the IF signal. The VGA includes a bank pair having a first bank of differential pairs of transistors and a second bank of differential pairs of transistors. The bank pair is cross-coupled in parallel, the IF signal is applied to the bank pair decoupled from a control signal used to control transconductance output gain of the bank pair over a range of input voltages. A digital IF demodulator is disposed on the substrate and coupled to the VGA for low voltage applications, for converting the IF signal to a demodulated baseband signal. And a transmitter is disposed on the substrate operating in cooperation with the receiver to establish a two way communications path.

Abstract: A protection circuit for extending the dynamic range of an amplifier circuit is described. Off-chip impedances, such as inductors, cause the output of the circuit to swing above and below the bias voltage. A protection circuit is included, either on-chip or off-chip, to protect the integrated circuit components if there is a fault condition in either of the off-chip impedances.

Abstract: A cache is coupled to receive an access which includes a cache allocate indication. If the access is a miss in the cache, the cache either allocates a cache block storage location to store the cache block addressed by the access or does not allocate a cache block storage location in response to the cache allocate indication. In one implementation, the cache is coupled to an interconnect with one or more agents. In such an implementation, the cache accesses may be performed in response to transactions on the interconnect, and the transactions include the cache allocate indication. Thus, the source of a cache access specifies whether or not to allocate a cache block storage location in response to a miss by the cache access. The source may use a variety of mechanisms for generating the cache allocate indication.

Abstract: A method for decoding an algebraic-coded message including determining a discrepancy indicator; determining an error locator polynomial according to a modified Berlekamp-Massey algorithm such that an uncorrectable message is detected; and producing a perceptible indication of the detected uncorrectable message. An apparatus includes storage devices, arithmetic components, and an uncorrectable message detector.

Abstract: A system includes an adaptive filter coupled to a communication channel. The adaptive filter includes a set of adaptive filter coefficients. A memory stores a predetermined set of filter coefficient thresholds. The filter coefficient thresholds may be indicative of channel faults or a length of the channel. A controller is configured to compare the set of filter coefficients to the predetermined set of filter coefficient thresholds. The controller is configured to determine the information about the channel based on compare results.

Abstract: An apparatus for processing a received signal includes an analog-to-digital converter (ADC) configured to produce a sampled signal from a received signal using a candidate sampling phase. An adaptive filter includes adaptive filter coefficients and is configured to receive the sampled signal and converge the filter coefficients based on the candidate sampling phase. A controller includes a module for comparing the converged filter coefficients to filter coefficient thresholds, and a module for determining a largest filter coefficient among one or more excessive filter coefficients that exceed one or more corresponding filter coefficient thresholds. The apparatus is stepped through multiple candidate sampling phases. A best sampling phase is selected based on the largest filter coefficients associated with the candidate sampling phases.

Abstract: A system including an agent and a memory controller, in which the agent may initiate transactions targeting a memory to which the memory controller is coupled and the transactions may include a page hint indication. The page hint indication is transmitted during the transaction by the agent, and may be an indication of whether or not the page addressed by the transaction should be kept open or closed. The memory controller may receive the page hint indication. When accessing the storage location(s) in the memory in response to the memory transaction, the memory controller may close the page or keep the page open responsive to the page hint indication.

Abstract: An apparatus for providing a programmable gain attenuator (PGA) while minimizing the influence of semiconductor switches on the signal being attenuated. An example apparatus comprises a impedance ladder with taps forming the junctions between impedances the PGA is then programmed by grounding the taps through terminating resistors.

Abstract: A biasing scheme for a MOSFET that mitigates the MOSFET body effect. The biasing scheme can be realized replicating the voltage at the source terminal of a MOSFET and applying this replicated voltage to the body terminal. In this manner, the effect of the body transconductance, at high frequencies, becomes a function of the ratio of the well-to-substrate capacitance of the MOSFET to the sum of the well-to-substrate capacitance and the source-to-body capacitance of the transistor. At high frequencies, the biasing scheme mitigates the reduction in gain of a source follower caused by the body effect of a driven MOSFET within the source follower, improves the stability of a feedback network established by a gain boosting amplifier and the driven MOSFET by contributing a negative half plane zero to the transfer function of the feedback network, and reduces the power consumed by the gain boosting amplifier.

Abstract: Present invention describes an efficient implementation of differential sensing in single ended DRAM arrays. According to one embodiment of the present invention, a respective local sense amplifier compares the accessed memory cell data with a dummy cell data in the opposite or adjacent block of the accessed block that is connected to a respective local bit line in the opposite block, amplifies the result of the comparison and puts the data on a global bit line. In one embodiment, the invention is process and temperature invariant using reference method and means for canceling cross coupling between read lines and write lines.

Abstract: An agent may be coupled to receive a clock signal associated with the bus, and may be configured to drive a signal responsive to a first edge (rising or falling) of the clock signal and to sample signals responsive to the second edge. The sampled signals may be evaluated to allow for the driving of a signal on the next occurring first edge of the clock signal. By using the first edge to drive signals and the second edge to sample signals, the amount of time dedicated for signal propagation may be one half clock cycle. Bandwidth and/or latency may be positively influenced. In some embodiments, protocols which may require multiple clock cycles on other buses may be completed in fewer clock cycles. For example, certain protocols which may require two clock cycles may be completed in one clock cycle. In one specific implementation, for example, arbitration may be completed in one clock cycle. Request signals may be driven responsive to the first edge of the clock signal and sampled responsive to the second edge.

Abstract: A circuit and method for bridging an analog signal between two integrated circuits operating at different supply voltages. The circuit is a two stage fixed gain amplifier. The first stage is a transconductance amplifier and the second stage is an operational amplifier. The first stage converts an input signal from a voltage into a current. The second stage converts the current signal to an output voltage signal.

Abstract: A modified ranging request in a broadband communications system. The modified ranging request includes a header, a management message header attached to the header, a management message payload attached to the management message header, and a CRC attached to the management message payload. The management message header enables bandwidth requests to be made by subscriber equipment without contention. The management message header also includes state of health information on the status of a downstream transmission for enabling a central location to determine how to assign subscribers to queues in an adaptive modulation scheme.

Abstract: An analog to digital converter includes a reference ladder, a track-and-hold amplifier tracking an input signal with its output signal during the phase &phgr;1 and holding a sampled value during, a coarse analog to digital converter having a plurality of coarse amplifiers each inputting a corresponding tap from the reference ladder and the output signal, a fine analog-to-digital converter having a plurality of fine amplifiers inputting corresponding taps from the reference ladder and the output signal, the taps selected based on outputs of the coarse amplifiers, a clock having phases &phgr;1 and &phgr;2, a circuit responsive to the clock that receives the output signal, the circuit substantially passing the output signal and the corresponding taps to the fine amplifiers during the phase &phgr;2 and substantially rejecting the output signal and the corresponding taps during the phase &phgr;1, and an encoder converting outputs of the coarse and fine amplifiers to an N-bit digital signal representing the input s

Abstract: Digital data signals at a variable input frequency are converted by a numerically controlled oscillator and an interpolator to a signal at a fixed output sampling frequency. The conversion of the variable input frequency to the fixed output sampling frequency may be by a factor other than an integer. The interpolated digital data signals at the fixed output sampling frequency are then modulated into a pair of trigonometric signals at a programmable carrier frequency, one signal having a cosine function and the other signal having a sine function. The modulated signals at the fixed output sampling frequency are then combined to create a modulated signal at a carrier frequency determined by the frequency of the sine and cosine signals. The modulated signal is sampled at the fixed output sampling frequency and converted to a corresponding analog signal using a digital-to-analog converter.

Abstract: An M-bit folding/interpolating analog-to-digital converter (ADC) circuit, comprising a reference voltage generator, a converter, an interpolator, an amplifying stage, a comparator, and an encoder. The converter has an amplifier that receives at least one of a plurality of first reference voltage signals and outputs a plurality of coarse bits. The converter also has N-number of folding blocks, which output a plurality of folded signals. Each folding block comprises a plurality of capacitors, a differential amplifier and a feedback element. The folded signals output by the converter are then interpolated, amplified, compared and output as a plurality of fine bits. The encoder receives the coarse and fine bits and outputs the digital signal.

Abstract: A system and method for executing previously created run time executables in a configurable processing element array is disclosed. In one embodiment, this system and method begins by identifying at least one subset of program code. The method may then generate at least one set of configuration memory contexts that replaces each of the at least one subsets of program code, the at least one set of configuration memory contexts emulating the at least one subset of program code. The method may then manipulate the the at least one set of multiple context processing elements using the at least one set of configuration memory contexts. The method may then execute the plurality of threads of program code using the at least one set of multiple context processing elements.