Abstract: A sub-quantizer for sub-quantization of a vector includes a sub-codevector generator that generates a set of candidate sub-codevectors, and transformation logic that transforms each candidate sub-codevector into a corresponding codevector. A memory stores an illegal space definition representing illegal vectors. A legal status tester determines legal codevectors among the codevectors based on the illegal space definition. An error calculator generates error terms corresponding to the candidate sub-codevector, and a sub-codevector selector determines a best one of the sub-codevectors corresponding to a legal codevector and a best error term. The vector includes parameters relating to a speech and/or audio signal, such as Line Spectral Frequencies (LSFs).

Abstract: A multiple layer inductor has a first spiral conductive pattern disposed on a first surface; a second spiral conductive pattern disposed on a second surface; a continuing interconnection coupled to the first and second spiral conductive patterns; an interface coupled to the first and second spiral conductive patterns; and a conductive shield pattern disposed on a third surface that is adjacent to the second surface. The interface includes a first terminal disposed on the first surface that is coupled to the first spiral conductive pattern. The interface also includes a second terminal that is disposed on the first surface and coupled to said second spiral conductive pattern.

Abstract: A method and system are provided for synthesizing a number of corrupted frames output from a decoder including one or more predictive filters. The corrupted frames are representative of one segment of a decoded signal (sq(n)) output from the decoder. The method comprises determining a first preliminary time lag (ppfe1) based upon examining a predetermined number (K) of samples of another segment of the decoded signal and determining a scaling factor (ptfe) associated with the examined number (K) of samples when the first preliminary time lag (ppfe1) is determined. The method also comprises extrapolating one or more replacement frames based upon the first preliminary time lag (ppfe1) and the scaling factor (ptfe).

Abstract: Methods and circuitry reduce adverse impacts of intermodulation and optimize performance of integrated circuits that include two or more oscillator circuits on the same chip. In one embodiment, intermodulation between voltage-controlled oscillators (VCOs)in the receiver and transmitter paths of a transceiver is reduced by adjusting relative power of the VCOs and/or bandwidths of the phase-locked loops (PLLs). The invention measures the injection lock frequency range of the VCOs based on which transmitter and receiver VCO power and loop bandwidths are adjusted.

Abstract: A transceiver includes a Downstream Signal Processor (DSP), an Upstream Signal Processor (USP), a Local Oscillator (LO), a differencer, a reference signal generator, and an estimator. The DSP receives an initial downstream signal, a downstream LO signal from the LO, and from the estimator a frequency-offset estimate indicative of a free-running frequency offset included in the initial downstream signal. The DSP uses the LO signal and the estimate to frequency down-convert the initial downstream signal, and also to remove the frequency offset from the initial downstream signal, thereby producing a corrected downstream signal. The USP uses both an upstream LO signal from the LO and the estimate to frequency convert an initial upstream signal so as to produce a frequency pre-corrected upstream signal.

Abstract: A device of dynamic communication of information allows, on the average, non-integer bits per symbol transmission, using a compact code set or a partial response decoding receiver. A stream of k or k+1 data bits is grouped into bit vectors which then are mapped onto corresponding signal constellations forming transmission symbols. Two or more symbols can be grouped and further encoded, so that a symbol is spread across the two or more symbols being communicated. Sequence estimation using, for example, maximum likelihood techniques, as informed by noise estimates relative to the received signal. Each branch metric in computing the path metric of a considered sequence at the receiver is weighted by the inverse of the noise power. It is desirable that the constellation selection, sequence estimation and noise estimation be performed continuously and dynamically.

Abstract: A method and apparatus for providing local control of processing elements in a network of multiple context processing element are provided. A multiple context processing element is configured to store a number of configuration memory contexts. This multiple context processing element maintains data of a current configuration. State information is received from at least one other multiple context processing element. At least one configuration control signal is generated in responses to the state information and the data of a current configuration. One of multiple configuration memory contexts is selected in response to the configuration control signal, the selected configuration memory context controlling the multiple context processing element. Each multiple context processing element in the networked array of multiple context processing elements has an assigned physical and virtual identification.

Abstract: A point-to-multipoint network interface is provided that is simpler and less costly to implement than conventional Ethernet switches. The interface includes a plurality of downstream transmitters for transmitting data packets to a plurality of end user devices, a plurality of downstream receivers for receiving data packets from the plurality of end user devices, an upstream transmitter and an upstream receiver. A multiplexer within the interface multiplexes data packets received from the end user devices into a stream of data packets for transmission to a higher level node regardless of the destination address of the data packets. Conversely, a demultiplexer within the interface demultiplexes a stream of data packets received from the higher level node into individual data packets for selective transmission to one of the plurality of end user devices. The interface can support asymmetrical transmission rates on the upstream and downstream channels between the interface and the end user devices.

Abstract: A phase locked loop circuit having a loop filter including a variable resistance for normal loop operation and for fast acquisition has improved stability by defining a loop pole separate from the loop filter. The loop pole remains constant during transition periods of the filter resistance. The loop pole remains constant while loop bandwidth is varied for either phase acquisition or normal operation, and the ratio of bandwidth to pole varies only linearly which makes the phase locked loop more stable during the bandwidth adjustment.

Abstract: A signal processing system which discriminates between voice signals and data signals modulated by a voiceband carrier. The signal processing system includes a voice exchange, a data exchange and a call discriminator. The voice exchange is capable of exchanging voice signals between a switched circuit network and a packet based network. The signal processing system also includes a data exchange capable of exchanging data signals modulated by a voiceband carrier on the switched circuit network with unmodulated data signal packets on the packet based network. The data exchange is performed by demodulating data signals from the switched circuit network for transmission on the packet based network, and modulating data signal packets from the packet based network for transmission on the switched circuit network. The call discriminator is used to selectively enable the voice exchange and data exchange.

Abstract: An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programable attenuation and a programable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator.

Abstract: An exemplary embodiment of the present invention described and shown in the specification and drawings is a transceiver with a receiver, a transmitter, a local oscillator (LO) generator, a controller, and a self-testing unit. All of these components can be packaged for integration into a single IC including components such as filters and inductors. The controller for adaptive programming and calibration of the receiver, transmitter and LO generator. The self-testing unit generates is used to determine the gain, frequency characteristics, selectivity, noise floor, and distortion behavior of the receiver, transmitter and LO generator. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or the meaning of the claims.

Abstract: Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C3MOS) logic fabricated in conventional CMOS process technology. An entire family of logic elements including inverter/buffers, level shifters, NAND, NOR, XOR gates, latches, flip-flops and the like are implemented using C3MOS techniques. Optimum balance between power consumption and speed for each circuit application is achieve by combining high speed C3MOS logic with low power conventional CMOS logic. The combined C3MOS/CMOS logic allows greater integration of circuits such as high speed transceivers used in fiber optic communication systems. The C3MOS structure enables the use of a power supply voltage that may be larger than the voltage required by the CMOS fabrication process, further enhancing the performance of the circuit.

Abstract: A modem receiver 10 receives a multitone signal with a cyclic extension of M samples on a channel 20. The receiver includes a time domain equaliser 14 that includes a finite impulse response (FIR) filter. The FIR filter targets the combined response of the channel and filter to a target impulse response having N taps, where N is less than M+1.

Abstract: A supervisory communications node monitors and controls communications with a plurality of remote devices throughout a widely distributed network. A method, system, and computer program product are provided to convey and maintain information used to synchronize the packetization and burst operations within the network. During session setup, jitter constraints indirectly are used to explicitly communicate a synchronization timing reference. The timing reference is set at the beginning of a phase/period boundary used to service the session. In an embodiment, the announcement of the first grant is used as an explicit indication of the synchronization timing reference value. In another embodiment, the synchronization timing reference value is inferred if a remote device receives contiguous voice grants meeting certain conditions. In an embodiment implementing periodic scheduling, the actual arrival of the first grant is used to infer the synchronization timing reference value.

Abstract: A method and apparatus to ensure DLL locking at a minimum delay is provided. In one embodiment, a DLL circuit includes a phase detector, a counter, a programmable delay line, and a counter control circuit. Upon initialization of the DLL circuit, the counter control circuit is configured to cause the counter to count increment, regardless of the phase relationship between a reference clock signal and the output clock signal. The counter continues incrementing, thereby changing the phase relationship between the reference clock signal and the output clock signal by adjusting the delay of the programmable delay line. This eventually results in a phase lock between the reference clock signal and the output clock signal at a minimum delay. Once the DLL achieves a phase lock between the reference clock signal and the output clock signal, the counter increments or decrements its count in order to maintain or re-acquire a lock.

Abstract: A memory-efficient convolutional interleaver/deinterleaver with a memory array, a write commutator, and a read commutator wherein the commutators perform their respective write and read operations relative to a preselected memory cell after a predetermined delay. The delay is chosen using a modulo-based technique, such that an efficient implementation: of a Ramsey Type-II interleaver is realized.

Abstract: A high-speed bank select multiplexer latch may be coupled to a pair of differential output nodes and configured to capture and retain an output on the pair of differential output nodes responsive to two or more pairs of differential data inputs being active. A first subcircuit including a first N-channel transistor and a second N-channel transistor is configured to receive at least a first input signal and a second input signal and to drive a first output on a first output node responsive to either of the first input signal or the second input signal being active. Additionally, a second subcircuit including a third N-channel transistor and a fourth N-channel transistor is configured to receive at least a third input signal and a fourth input signal and to drive a second output on a second output node responsive to either of the third input signal or the fourth input signal being active.

Abstract: All PMOS (p channel metal oxide semiconductor) fully differential voltage controlled oscillator (VCO). A fully differential implementation within the present invention provides for a very effective rejection of common mode noises. In addition, the PMOS implementation of the present invention allows for a substantial reduction in 1/f noise. The PMOS fully differential VCO may be employed within phase locked loops (PLLs) and other applications that require a very clean signal (with very low noise) and that must be operable at very high frequencies. The present invention enables a very compact design, thereby minimizing extraneous noise pickup. The device may be over-driven with a higher power supply than is commonly used in prior art VCOs; the over-driving provides for a higher transconductance gm from the PMOS device enabling higher gain. A center-tapped inductor is shunted to ground in a manner that does not reduce the inductor's quality factor Q.

Abstract: A system and method is presented to utilize hardware instead of software to compare for bandwidth request changes between two consecutively received unsolicited grant service (UGS) extended headers for the same service identifier (SID), obtains significant savings in CPU cycles for the CMTS software. The system determines whether adequate bandwidth is being provided from a cable modem termination system to a data provider during a unsolicited grant service flow. The system includes a means for receiving a current voice packet in the unsolicited grant service flow at the cable modem termination system from the data provider, where the current voice packet comprises a unsolicited grant service extended header. The system further includes means for comparing the current unsolicited grant service extended header with a previous unsolicited grant service extended header.