Abstract: A system and method is presented to utilize hardware instead of software to compare for bandwidth request changes between two consecutively received unsolicited grant service (UGS) extended headers for the same service identifier (SID), obtains significant savings in CPU cycles for the CMTS software. The system determines whether adequate bandwidth is being provided from a cable modem termination system to a data provider during a unsolicited grant service flow. The system includes a means for receiving a current voice packet in the unsolicited grant service flow at the cable modem termination system from the data provider, where the current voice packet comprises a unsolicited grant service extended header. The system further includes means for comparing the current unsolicited grant service extended header with a previous unsolicited grant service extended header.

Abstract: Improved carrier recovery, symbol timing, and carrier phase tracking systems and methods suitable for use in connection with a dual-mode QAM/VSB receiver system are disclosed. Carrier and phase recovery systems operate on complex signals representing symbols having the same time stamp for each phase error term. in-phase signals are sampled twice a symbol at the in-phase symbol sampling time and at the quadrature-phase symbol sampling time. The signals are de-multiplexed to generate I and XI data streams, where I represents the in-phase sampling time signals and XI represents mid-symbol point sample times. A similar procedure is carrier out on quadrature-phase signals. When the in-phase signal is de-multiplexed to generate a symbol I, the quadrature-phase signal is de-multiplexed to generate its mid-symbol point XQ. Both I and Q are decoded in a decision device to define a symbol error term, which is combined with the opposite mid-symbol signal to define a phase error term PI and PQ for each rail.

Abstract: A method and system for dropping lower priority packets for transmission over a communication medium is provided. A cable modem termination system receives one or more packets to be transferred to one or more data providers, each packet having a priority. Then, based on the priority, a media access controller stores each of the packets in one or more priority queues in a fixed shared memory space in such a way as to maintain the order in which the packets were received in each of the priority queues. The media access controller monitors the number of packets in each of the priority queues and signals an interrupt when a packet threshold is exceeded in one or more of the priority queues. The media access controller then drops lower priority packets in the fixed shared memory space based on the order received to guarantee that there is enough memory to store higher priority packets in the fixed shared memory space.

Abstract: A media access controller (MAC) is configured with a DOCSIS Header creator circuit. The DOCSIS header creator circuit is configured with logic for receiving a data packet and determining whether the received data packet has an existing packet header prepended thereto. The DOCSIS header creator circuit is further configured to determine if the length of the received data packet includes a cyclic redundancy code. Still further, the DOCSIS header creator circuit is configured to determine a packet header length field value for the received data packet. If the DOCSIS header creator circuit determines that a cyclic redundancy code needs to be included in with the received data packet, then the DOCSIS header creator circuit is able to generate a CRC flag. If the data packet needs to be encrypted, then the DOCSIS header creator circuit will generate an encryption flag if it is determined that the received data packet should be encrypted.

Abstract: There is disclosed a system for designing circuits which involves pre-placing delay elements between circuit components susceptible to shoot-through due to effects of clock skew, each delay element having a physical form and at least one input terminal and at least one output terminal; determining which delay elements are not critical in preventing shoot-through; removing non-critical delay elements from the circuit; and replacing each removed delay element with a cell having a physical form equivalent to the physical form of the removed delay element and a wire connection between an input and an output of the cell equivalent to an input and output of the delay element. This wire cell has the effect of removing the delay element from the circuit without having to reposition the circuit components. This has the result that it is not necessary to re-position circuit components on the removal of delay elements and then to re-evaluate the circuit performance. Circuit design can be significantly improved.

Abstract: A supervisory communications device, such as a headend device within a cable communications network, monitors and controls communications with a plurality of remote communications devices, such as cable modems, throughout a widely distributed network, including the Internet. The supervisory device establishes the upstream slot structure and allocates upstream bandwidth by sending UCD and MAP messages over its downstream channel. The supervisory device also uses the MAP messages and minislot counts to anticipate bursts from the remote devices. Dual registers are provided within the supervisory device to generate minislot counts. A primary register generates minislot counts for a current slot structure, and a secondary register generates minislot counts for a revised slot structure. Software executed on the supervisory device determines a switchover time for changing to the revised slot structure and revised minislot count.

Abstract: A system and method for synchronizing multiple cable modem termination system (CMTS) devices is provided. In an embodiment, a calibration pulse issued from a calibration pulse generator is received by one or more CMTS devices. Upon receiving the calibration pulse, each CMTS device stores the present value of a counter. Next, each slave CMTS device generates and stores a future time stamp value. The future time stamp value represents a future time when each slave CMTS device will update the value of its counter. When the future time stamp value stored in a particular CMTS device is equal to the value of the CMTS devices counter, an internal signal will be issued by the CMTS device. Upon issuance of the internal signal, the counter of each of the one or more slave CMTS devices is synchronized with one another by resetting each counter to a previously stored new counter value.

Abstract: A supervisory communications device, such as a headend device within a cable communications network, monitors and controls communications with a plurality of remote communications devices, such as cable modems, throughout a widely distributed network. The supervisory device allocates bandwidth on the upstream channels by sending MAP messages over its downstream channel. A highly integrated media access controller integrated circuit (MAC IC) operates within the headend to provide lower level DOCSIS processing on signals exchanged with the remote devices. The enhanced functionality of the MAC IC relieves the processing burden on the headend CPU and increases packet throughput. The enhanced functionality includes header suppression and expansion, DES encryption and decryption, fragment reassembly, concatenation, and DMA operations.

Abstract: Electrically, mechanically, and thermally enhanced ball grid array (BGA) packages are described. A substrate has a surface, wherein the surface has an opening therein. A stiffener has a surface coupled to the surface of the substrate. An area of the surface of the stiffener can be greater than, equal to, or less than an area of the surface of the substrate. A thermal connector is coupled to the surface of the stiffener through the opening. A surface of the thermal connector is capable of attachment to a printed circuit board (PCB) when the BGA package is mounted to the PCB. The thermal connector can have a height such that the thermal connector extends into a cavity formed in a surface of the PCB when the BGA package is mounted to the PCB. Alternatively, the stiffener and thermal connector may be combined into a single piece stiffener, wherein the stiffener has a protruding portion.

Abstract: The present invention provides apparatus and methods for performing payload header suppression (PHS), expansion, and verification in hardware. A PHS verify circuit reads a data packet until it reaches the location where the first byte must be compared to PHS rule verify bytes. Next, all the relevant bytes in the payload header are compared to the PHS rule verify bytes obtained from a payload header suppression rule mask. Upon completion of the compare, a flag is generated to a PHS suppress circuit indicating that verification has passed or failed. For payload headers passing the verification process, the payload header suppress circuit examines the payload header suppression mask to identify one or more bits in the payload header for which an associated byte string is to be suppressed. Next, the associated byte string for each of the identified bits are suppressed to generate a suppressed packet payload header. Finally, a payload header suppression index is added to the suppressed packet payload header.

Abstract: A method and system described for producing frequency multiplication/division by any non-integer output signal frequency relative to a reference signal frequency of a PhaseLock-Loop (PLL), while simultaneously maintaining low jitter.

Abstract: A ROM or other memory may include two or more partitions and a precharge circuit. Each of the partitions may be coupled to separate sets of output conductors, to which the precharge circuit may be coupled. The precharge circuit may precharge the conductors of the partition to be read, while not precharging the other conductors. In one embodiment, the precharge may be to a voltage representing a binary value. In one implementation, the non-precharged conductors may be held to a predetermined voltage different from the voltage to which the precharged conductors are precharged. The predetermined voltage may represent the opposite binary value to the binary value represented by the precharge voltage. The ROM may also include an output circuit which may, in certain embodiments, comprise a logic circuit which logically combines the signals on respective conductors from each partition to provide output signals from the ROM.

Abstract: A video and graphics system uses multiple transport processors to receive compressed data streams to perform PID and section filtering as well as DVB and DES decryption and to demultiplex them. The compressed data streams may include in-band and out-of-band MPEG Transport streams. The video and graphics system processes the PES into digital audio, MPEG video and message data. A core transport processor includes a PCR recovery module for extracting PCRs contained in the compressed data streams and for providing the extracted PCRs to a video transport processor and an audio decode processor. The PCR recovery module has a direct load capability for receiving user defined PCRs and outputting them instead of outputting the extracted PCRs. The PCR recovery module extracts PCRs from both MPEG Transport streams and DIRECTV transport streams.

Abstract: A programmable gain amplifier (PGA) has an amplifier and a variable resistor that is connected to the output of the amplifier. The variable resistor includes a resistor that is connected to a reference voltage and multiple parallel taps that tap off the resistor. A two-stage switch network having fine stage switches and coarse stage switches connects the resistor taps to an output node of the PGA. The taps and corresponding fine stage switches are arranged into two or more groups, where each group has n-number of fine stage switches and corresponding taps. One terminal of each fine stage switch is connected to the corresponding resistor tap, and the other terminal is connected to an output terminal for the corresponding group. The coarse stage switches select from among the groups of fine stage switches, and connect to the output of the PGA.

Abstract: A method for decoding an algebraic-coded message including determining a discrepancy indicator; determining an error locator polynomial according to a modified Berlekamp-Massey algorithm such that an uncorrectable message is detected; and producing a perceptible indication of the detected uncorrectable message. An apparatus includes storage devices, arithmetic components, and an uncorrectable message detector.

Abstract: A method and system are provided for removing discontinuities associated with synthesizing a corrupted frame output from a decoder including one or more predictive filters. The corrupted frame is representative of one segment of a decoded signal. The method comprises copying a first number of stored samples of the decoded signal in accordance with a time lag and a scaling factor, and calculating a first number of ringing samples output from at least one of the filters.

Abstract: Methods and circuitry for implementing high speed first-in first-out (FIFO) structures. In one embodiment, a FIFO is disclosed that allows the frequency of one clock, e.g., the write clock, to be different than (e.g., half) that of the other (read) clock. In another embodiment a FIFO is presented that can be set and/or reset asynchronously. Other embodiments are disclosed wherein the read and write pointers are effectively monitored to ensure proper timing relationship, to detect loss of clock as well as to detect other abnormal FIFO conditions.

Abstract: A startup protocol is provided for use in a communications system having a communications line with a master transceiver at a first end and a slave transceiver at a second end, each transceiver having a noise reduction system, a timing recovery system and at least one equalizer all converging at startup of the system. The operation of the startup protocol is partitioned into stages. The first stage includes the step f converging the equalizer and the timing recovery system of the slave while converging the noise reduction system of the master. Upon completion of the first stage the protocol enters a second stage which includes the step of converging the equalizer and the timing recovery system of the master, converging the noise reduction system of the slave, freezing the timing recovery system of the slave, and resetting the noise reduction system of the master.

Abstract: The present invention provides an overflow detector for a FIFO. The FIFO includes a plurality of registers each having an input and an output, a plurality of write signals each respectively coupled to a clock, one of the plurality of registers, and a plurality of read switches each respectively coupled to an output of one of the plurality of registers, each of the plurality of read switches being controlled by a respective read signal. The overflow detector includes a plurality of clocked registers each of which is coupled to receive a write signal and its corresponding read signal, wherein each clocked register records a read signal and is clocked by the corresponding write signal.

Abstract: A signal sensing module senses an RF signal and produces one or more secondary signals representative of the RF signal. An impedance matching control module generates a control signal, based on the one or more secondary signals, which is indicative of an impedance mismatch between a load and a communications device. The control signal is then applied to at least one variable impedance device to adjust the impedance of an impedance matching network and thereby reduce the impedance mismatch between the load and the communications device. In an embodiment, the at least one variable impedance device is a barium strontium titanate, thin film, parallel plate capacitor. In other embodiments, other variable impedance devices such as other types of thin film capacitors or varactor diodes are be used to adjust the impedance of the impedance matching network.