Abstract: A graphics display system integrated circuit is used in a set-top box for controlling a television display. The graphics display system processes analog video input, digital video input, and graphics input. The system incorporates a unified memory architecture that is shared by the graphics system, a CPU, and other peripherals. The unified memory architecture uses real time scheduling to service tasks. Critical instant analysis is used to find a schedule for memory usage that does not affect memory requirements of real time tasks while at the same time servicing non-real-time tasks as needed.

Abstract: A method of executing instructions in a computer system on operands containing a plurality of packed objects in respective lanes of the operand is described. Each instruction defines an operation and contains a condition setting indicator settable independently of the operation. The status of the condition setting indicator determines whether or not multibit condition codes are set. When they are to be set, they are set depending on the results of carrying out the operation for each lane.

Abstract: Methods and apparatus are provided for generating interrupts associated with the completion of data processing. An external host may pass a first data block to a first processing engine and later pass a second data block to a second processing engine. In typical implementations, the external host expects that processing of the first data block completes first. To prevent errors and faults on the part of the external host, an interrupt associated with the processing of the second data block completing first is collapsed onto the first data block.

Abstract: A method and an apparatus for retiming in a network of multiple context processing elements are provided. A programmable delay element is configured to programmably delay signals between a number of multiple context processing elements of an array without requiring a multiple context processing element to implement the delay. The output of a first multiple context processing element is coupled to a first multiplexer and to the input of a number of serially connected delay registers. The output of each of the serially connected delay registers is coupled to the input of a second multiplexer. The output of the second multiplexer is coupled to the input of the first multiplexer, and the output of the first multiplexer is coupled to a second multiple context processing element. The first and second multiplexers are provided with at least one set of data representative of at least one configuration memory context of a multiple context processing element.

Abstract: A method and circuit for adjusting clock pulse widths in a high speed sample and hold circuit. A single phase clock signal is input into a pulse discriminator and separated into rising and falling edges. The edges are adjusted to a desired slope. The adjusted edges and the unadjusted edges are summed and output as multiple clock signals with a desired pulse edge alignment. The clock signals control switches in a manner to reduce signal dependent sampling distortion.

Abstract: Various circuit techniques employ a transconductance (gm) cell in control loops to implement circuits such as phase locked loops and delay locked loops that are capable of operating at ultra high frequencies with improved precision and noise performance. The gm cell is designed to operate on an analog input signal with a very small swing and more gradual transition edges. These characteristics allow implementation of high frequency circuits and systems including, for example, transceivers for fiber optic channels, disk driver electronics and the like.

Abstract: A system including an agent and a memory controller, in which the agent may initiate transactions targeting a memory to which the memory controller is coupled and the transactions may include a page hint indication. The page hint indication is transmitted during the transaction by the agent, and may be an indication of whether or not the page addressed by the transaction should be kept open or closed. The memory controller may receive the page hint indication. When accessing the storage location(s) in the memory in response to the memory transaction, the memory controller may close the page or keep the page open responsive to the page hint indication.

Abstract: Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C3MOS) logic with inductive broadbanding fabricated in conventional CMOS process technology. Optimum balance between power consumption and speed for each circuit application is achieve by combining high speed C3MOS logic with inductive broadbanding/C3MOS logic with low power conventional CMOS logic. The combined C3MOS logic with inductive broadbanding/C3MOS/CMOS logic allows greater integration of circuits such as high speed transceivers used in fiber optic communication systems.

Abstract: An integrated receiver with channel selection and image rejection is substantially implemented on a single CMOS integrated circuit. A receiver front end provides programable attenuation and a programable gain low noise amplifier. LC filters integrated onto the substrate in conjunction with image reject mixers provide image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. Active filters utilize multi track spiral inductors with shields to increase circuit Q. Frequency planning provides additional image rejection. Local oscillator signal generation methods on chip reduce distortion. A PLL generates needed out of band LO signals. Direct synthesis generates in band LO signals. PLL VCOs are centered automatically. A differential crystal oscillator provides a frequency reference. Differential signal transmission throughout the receiver is used. ESD protection is provided by a pad ring and ESD clamping structure.

Abstract: The present invention relates to a one-time programmable memory cell and a method of setting a state for a one-time programmable memory cell. The memory cell includes a storage element adapted to store data and two thin gated fuses coupled to the storage element, adapted to set the state of the memory cell. A level shifter device is connected to the gated fuses and is adapted to stand off a high voltage when setting the state of the memory cell. At least one switch transistor is connected to at least the level shifter device and is adapted to select at least one of the gated fuses, enabling a high voltage to be communicated thereto, thus setting the state of the memory cell. A programming device is coupled to the storage element and is adapted to keep at least one of the gated fuses low when setting the state of the memory cell.

Abstract: A method for testing a semiconductor wafer. An array of probes is coupled to the semiconductor wafer. Then a voltage difference is applied across a plurality of adjacent metal line pairs (e.g., wordline and/or bitline pairs) of one or more SRAM arrays of at least one die. Application of the voltage difference induces failure of metal stringers or defects between the adjacent lines. Additionally, the voltage can be applied across respective pairs of substantially all parallel metal lines of the one or more SRAM arrays of more that one die of the semiconductor wafer.

Abstract: Method and circuitry for converting a differential logic signal to a single-ended logic signal that minimize delay. In specific embodiments differential logic signals of the type employed in, for example, current-controlled complementary metal-oxide-semiconductor (C3MOS) logic are converted to single-ended rail-to-rail CMOS logic levels using the regenerative action of a CMOS latch.

Abstract: A method of concealing bit errors in a signal is provided. The method comprises encoding a signal parameter according to a set of constraints placed on a signal parameter quantizer. The encoded signal parameter is decoded and compared against the set of constraints. Finally, the method includes declaring the decoded signal parameter invalid when the set of constraints is violated.

Abstract: An active splitter circuit arrangement includes a first amplification module having a number of first input ports and first output ports. The first amplification module is configured to provide first stage amplification to a received input signal and produce from the amplified input signal a number of output signals, each substantially matching the input signal. Also included is a first gain control device having a number of gain input ports respectively coupled to the first output ports and a gain output port coupled to at least one of the first input ports. The first gain control device is configured to control a gain of the first amplification module. Next, a number of second amplification modules corresponding to the number of output signals has a number of second input ports respectively coupled to the first output ports.

Abstract: A semiconductor wafer configured for in-process testing of integrated circuitry fabricated thereon. At least two die are separated by a scribe area, and each of the die has at least one complementary metal oxide silicon (CMOS) static random access memory (SRAM) array embedded therein among mixed-signal CMOS circuitry. The mixed-signal CMOS circuitry includes devices with larger feature sizes compared to similar devices of the embedded SRAM array. A first process control monitor (PCM) testline is included, which has a first layout corresponding to the mixed-signal CMOS circuitry. Additionally, a second PCM testline is included, which has a second layout corresponding to the embedded SRAM arrays. The first and second PCM testlines are formed in the scribe area.

Abstract: Provided is a method and system for producing a drive signal for a current steering amplifier. An exemplary method comprises receiving a supply voltage signal and a differential input signal as a circuit input. A differential amplifier drive signal is produced in response to the received supply voltage signal, the received differential input signal, and the received differential control signal. The received differential input signal is adjusted to a value where magnitudes of negative and positive components of the differential control signal become equal to one another and are within a predetermined amount of a magnitude of the supply voltage signal.

Abstract: Provided is a system for implementing gain control in an amplification module comprising a first stage amplifier having a number of first stage input and output ports. The first stage amplifier is configured to provide first stage amplification to a received input signal and produce from the amplified input signal a number of output signals. Also included are a number of second stage amplifiers, each having second stage input and output ports, the second stage input ports being respectively coupled to the first stage output ports and being configured to receive the number of output signals. A gain control device is coupled to at least one from the group including the first stage input ports, the first stage output ports, and the second stage output ports. The gain control device is also configured to control a gain of at least one of the first stage amplifier and one or more of the number of second stage amplifiers.

Abstract: A circuit, system, and method are provided for imparting improved randomness into the selection of components or elements of a data converter, such as a D/A converter. The elements are intended to be of equal value, however, regardless of whether they are or not. A circuit is used to randomly select subsets of elements according to a bi-directional selection technique in order to effectively rending the elements or components of equal value. Associated with each component is a switch, and a subset of the plurality of components are correspondingly switched in successive order progressing in a first direction and, subsequently, in successive order progressing in a second direction opposite the first direction. Connecting components in a first direction from left-to-right follows by selecting components in a second direction from right-to-left, and then again selecting components in the first direction from left-to-right, and so forth.

Abstract: Binary indications are converted to an analog representation with significant reduction in ringing at the transitions between successive binary indications and in the period during each binary indication. The binary indications are disposed in a row-and-column matrix to provide a thermometer code. Each stage of the converter includes a decoder and latch arranged so the decoder inputs settle before the latch is set by the clock pulses. The stages are implemented in complementary CMOS. Complementary transistors are biased so one transistor of the pair is driven to the rail while the other transistor of the pair floats. A dummy CMOS transistor is used to balance the number of transistors in the decoder paths.

Abstract: A high-speed bank select multiplexer latch may be coupled to a pair of differential output nodes and configured to capture and retain an output on the pair of differential output nodes responsive to two or more pairs of differential data inputs being active. A first subcircuit including a first N-channel transistor and a second N-channel transistor is configured to receive at least a first input signal and a second input signal and to drive a first output on a first output node responsive to either of the first input signal or the second input signal being active. Additionally, a second subcircuit including a third N-channel transistor and a fourth N-channel transistor is configured to receive at least a third input signal and a fourth input signal and to drive a second output on a second output node responsive to either of the third input signal or the fourth input signal being active.