Abstract: Continuously tuning a transconductance. Coupling a degeneration resistance from a first source of a first transistor in a differential pair of transistors to a second source of a second transistor in the differential pair of transistors. Applying a second variable degeneration resistance in parallel to the first degeneration resistance in response to the application of a first variable control voltage. And applying a third variable degeneration resistance in parallel to the first degeneration resistance and the second degeneration resistance in response to the application of a second variable control voltage having a fixed voltage offset from the first variable control voltage.

Abstract: Provided is an architecture for a cryptography accelerator chip that allows significant performance improvements over previous prior art designs. In various embodiments, the architecture enables parallel processing of packets through a plurality of cryptography engines and includes a classification engine configured to efficiently process encryption/decryption of data packets. Cryptography acceleration chips in accordance may be incorporated on network line cards or service modules and used in applications as diverse as connecting a single computer to a WAN, to large corporate networks, to networks servicing wide geographic areas (e.g., cities). The present invention provides improved performance over the prior art designs, with much reduced local memory requirements, in some cases requiring no additional external memory. In some embodiments, the present invention enables sustained full duplex Gigabit rate security processing of IPSec protocol data packets.

Abstract: The invention provides apparatus and a method of scan testing digital logic circuits, in particular faults in circuit operation during operational transitions in the circuit. The system is intended for use in testing a logic circuit which is driven by high frequency oscillating means and an external clock, which external clock during normal operation is used to time control of the operation of the circuit; system disabling the external clock, synchronising testing means with the internal oscillating means, performing testing on the circuit while the external clock is disabled and re-enabling the external clock following testing. In the preferred embodiment, the test clock is synchronised with a PLL. The preferred embodiments address the difficulties with the conventional test methodology by synchronising the test clock with the phase locked loop internal to the IC.

Abstract: A system and method for management of bandwidth in a fiber optic, ethernet-based, TDMA communications system. A request/grant process is used to control the use of upstream bandwidth. A sense of time must therefore be shared by a headend and remote end-user devices. The invention provides for a gigabit media-independent interface in a media access controller to detect start-of-frame delimiters in incoming data. This allows for synchronization of a headend and end-user devices. The invention also allows for phase locking a transmit bit rate, at a headend, to the headend's clock. Transmitted data can the be used downstream to derive a local clock. Synchronization can also be maintained by the use of synchronization bytes in MPEG frames and/or variable length frames. Efficient bandwidth usage can also be facilitated by the use of maximum data units in allocating bandwidth in unsolicited grants, and by allowing flexible fragmentation and/or prioritization of internet protocol (IP) packets.

Abstract: A decode circuit for selecting one of a plurality of output lines in dependence on the status of a plurality of input lines, the circuit comprising: a first decode arrangement comprising: a first decode node; first precharging circuitry for charging the first decode node to a charging potential; first discharging circuitry comprising a plurality of switching means each operable in dependence on the status of a respective one of the input lines to couple the first decode node to a discharging potential; and first selection circuitry coupled to a respective one of the output lines and operable in response to a first enable signal to select that output line if the first decode node has not discharged; and a second decode arrangement comprising: a second decode node; second precharging circuitry for charging the second decode node to a charging potential; second discharging circuitry comprising a plurality of switching means each operable in dependence on the status of a respective one of the input lines to coupl

Abstract: A fiber optic, ethernet-based, TDMA communications system that addresses issues of cost, quality of service, and operational efficiency. An aggregating optical node is placed between a hub and end users. This allows the use of less expensive lasers, and permits a variety of connection topologies (e.g., fast ethernet point-to-point, shared broadcast, and gigabit ethernet) between the optical node and the end users. The use of an optical node also allows allocation of certain functions (e.g., bandwidth allocation) to the optical node. Moreover, an adaptive equalizer can be used in conjunction with any laser in the system to improve its signal to noise ratio.

Abstract: A system for management of bandwidth, cost control, and operational efficiency in a fiber optic, ethernet-based, TDMA communications system. The invention features an aggregating optical node between a central office and end users. The optical spectrum is divided according to end user, direction (i.e., upstream or downstream), and/or according to function (e.g., video or non-video). In an embodiment of the invention, a wavelength coupler can be used to couple multiple upstream wavelengths from respective end-user devices, for forwarding to a central office. Moreover, adaptive equalization can be used for noise cancellation purposes.

Abstract: A system, method, and computer program product for management of bandwidth, quality of service, and operational efficiency with respect to delivery of video in a fiber optic, ethernet-based, TDMA communications system. An optical node is placed between a hub and the user, and functionality is placed at the optical node to facilitate the provision of user services. The invention allows improved access to video by buffering a sequence of frames at the optical node. When a user accesses a channel part way through a transmission, a group of pictures starting with the initial frame will be available, and no frames will have been missed. Moreover, the function of responding to a user's command to switch channels is placed at the optical node, instead of at a more distant hub. This improves responsiveness to such commands. Also, when a user repeatedly attempts to access different sequences of frames (“channel surfing”), the optical node will detect such repeated access.

Abstract: A signal processing system which discriminates between voice signals and data signals modulated by a voiceband carrier. The signal processing system includes a voice exchange, a data exchange and a call discriminator. The voice exchange is capable of exchanging voice signals between a switched circuit network and a packet based network. The signal processing system also includes a data exchange capable of exchanging data signals modulated by a voiceband carrier on the switched circuit network with unmodulated data signal packets on the packet based network. The data exchange is performed by demodulating data signals from the switched circuit network for transmission on the packet based network, and modulating data signal packets from the packet based network for transmission on the switched circuit network. The call discriminator is used to selectively enable the voice exchange and data exchange.

Abstract: A compensation circuit compensates for the variation in the internal resistance of a multi-track inductor over temperature. The compensation circuit includes a dummy inductor that has the same temperature dependent resistance as that of the multi-track inductor that is to be compensated. A first field effect transistor is placed in series with the multi-track inductor that is to be compensated, and a second field effect transistor is placed in series with the dummy inductor, where the gates of the FETs are tied together. A control circuit provides a constant current for the dummy inductor and detects any changes in voltage of the dummy inductor over temperature. The control circuit includes a feedback loop that controls the gate voltage of both first and second FETs so as to compensate for the temperature dependent inductor resistance variations of both the dummy inductor and the multi-track inductor that is to be compensated.

Abstract: A method and apparatus to ensure DLL locking at a minimum delay is provided. In one embodiment, a DLL circuit includes a phase detector, a counter, a programmable delay line, and a counter control circuit. Upon initialization of the DLL circuit, the counter control circuit is configured to cause the counter to count increment, regardless of the phase relationship between a reference clock signal and the output clock signal. The counter continues incrementing, thereby changing the phase relationship between the reference clock signal and the output clock signal by adjusting the delay of the programmable delay line. This eventually results in a phase lock between the reference clock signal and the output clock signal at a minimum delay. Once the DLL achieves a phase lock between the reference clock signal and the output clock signal, the counter increments or decrements its count in order to maintain or re-acquire a lock.

Abstract: A computer system for conditionally performing an operation defined in a computer instruction, an execution unit of the computer system comprises at least one operand store for holding operands on which an operation defined in an instruction is to be performed, wherein said operand store defines a plurality of lanes each holding an object, a plurality of operators associated respectively with the lanes for carrying out an operation specified in an instruction on objects in the operand lanes, a destination store for holding objects resulting from the operation on a lane by lane basis, a plurality of control stores each comprising a plurality of indicators to control for each lane whether or not an operation defined in an instruction is to be performed on that lane, and control circuitry for controlling which of said plurality of control stores is to be used to control per lane execution of an instruction, the control circuitry being operative to select a control store from the plurality of control stores based

Abstract: A system and method for converting an analog input signal to a N-bit digital output signal. The invention comprises generating a plurality of reference voltage signals; pre-amplifying, separately, a difference between each of the plurality of reference voltage signals and an analog input signal using a plurality of cascaded, differential, switched-capacitor circuits to output a plurality of pre-amplified difference signals; and determining a zero-crossing result for each of the plurality of pre-amplified difference signals. Then one of a binary 1 and a binary 0 are assigned to each of the compared, pre-amplified signals. The binary 1's and 0's are encoded as an M-bit encoded signal, which is then decoded to output an N-bit digital output signal, wherein M is less that or equal to N.

Abstract: An address device simultaneously provides a first address to a first memory section using a first address bus and a second, incrementally higher, address to a second memory section using a second address bus. A buffer can then read from or write to the first and second memory sections. During a read operation, the buffer can receive a first portion of a misaligned data word from the first memory section and read a second portion of the misaligned data word from the second memory section and assemble the data in the data word from the first and second portions. When the access operation is a write operation, the buffer can effectively perform a shift operation on the data in the data word, then write a first portion of the word to the first memory section and write a second portion of the word to the second memory section. Accordingly, data accesses that would take two memory-access cycles on a conventional memory system are reduced to a single memory-access cycle.

Abstract: A system, method and computer program product is provided for mitigating the effects of burst noise on packets transmitted in a communications system, wherein each packet includes two or more FEC blocks. A receiving device implements an FEC block reconstruction technique to restore FEC blocks that have been corrupted by burst noise. In accordance with this technique, the receiving device receives some but not all of the FEC blocks of a transmitted packet. The receiving device then replaces the bad FEC blocks with good FEC blocks from a repeated packet transmission, if repetition outer coding is used, or by requesting retransmission of the bad FEC blocks or the entire original packet from a transmitting device, if a retransmission technique is used. A combination of repetition coding, retransmission, and FEC block reconstruction may also be used.

Abstract: Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C3MOS) logic fabricated in conventional CMOS process technology. An entire family of logic elements including inverter/buffers, level shifters, NAND, NOR, XOR gates, latches, flip-flops and the like are implemented using C3MOS techniques. Optimum balance between power consumption and speed for each circuit application is achieve by combining high speed C3MOS logic with low power conventional CMOS logic. The combined C3MOS/CMOS logic allows greater integration of circuits such as high speed transceivers used in fiber optic communication systems.

Abstract: First and second address-selection information, as well as first and second read/write information, is contemporaneously provided to various enabling circuits. The enabling circuits can then enable one or more first memory cells based on the first address-selection and first read/write information, and further enable the one or more second memory cells based on the second address-selection information and read/write information. Data can then be written to, or read from, the enabled memory cells in a single memory-access cycle.

Abstract: System for measuring a thickness of a circuit component on a printed circuit board (PCB). The system includes a first circuit, a power plane, a power strip, a calibration strip, a temperature sensor, and a second circuit. The power plane is coupled to the first circuit. The power strip is for providing power to the power plane and is disposed in the PCB connected to the power plane. The power strip has at least two vias. The calibration strip has a predetermined width and is disposed in said PCB. The calibration strip has at least two vias for measuring a voltage drop. The temperature sensor is coupled to the calibration strip and configured to measuring a temperature of the calibration strip. The second circuit is coupled to the temperature sensor and configured to determine the thickness of the calibration strip based on at least the temperature of the calibration strip.

Abstract: A current source DAC has calibration of the current sources used for providing the analog output. There are two outputs, one of which provides the output current or else a differential output is provided. The calibration is cyclic and the current source outputs switched to the output terminals are selected as a function of the point within the calibration cycle. The current stage of the cyclic calibration process is thus taken into account in the D/A conversion. For example, the average time since calibration for all current sources having outputs switched to the first output may be approximately equal to the average time since calibration for all current sources having outputs switched to the second output. In this way, the average current of the cells switched to one terminal is identical to the average current of the cells switched to the other terminal, and the average current of the cells switched to each terminal remains constant in time irrespective of the digital signal value being converted.

Abstract: Various systems and methods providing signal delay compensation for circuits such as a multi-pair gigabit Ethernet transceiver are disclosed. In an analog implementation a buffer with an adjustable delay may be used to minimize the delay mismatch between clock trees. The delay of the adjustable-delay buffer is controlled by bias voltages that determine the charging and discharging current to the adjustable buffer. A phase detector circuit is used to compare the clock phases for rising and falling edges, and to adjust the bias voltages that control these edges. In a digital implementation a selector switch, responsive to a phase detector, may be used to route clock signals through circuit elements to delay clock signals.