Abstract: A graphics display system integrated circuit processes analog video input, digital video input, and graphics input. The system incorporates a graphics accelerator that includes memory for graphics data. The accelerator preferably includes a coprocessor for performing vector type operations on a plurality of components of one pixel of the graphics data. The accelerator also includes an expanded instruction set for storing and loading data.

Abstract: Method and apparatus for determining the stopping point of an iterative decoding process. In one embodiment the estimated values of an iteration of an iterative decoder are provided to a signature circuit. If the signature does not differ from the previous signature developed from a prior iteration, or the signature developed from an iteration prior to the previous iteration, the decoding stops. The variance may also be tested and compared to a threshold as a criteria to stop the iterative decoding.

Abstract: A method of conditionally executing branch instructions which comprise an opcode field defining a type of test to be applied to determine whether or not to execute a branch operation, a control field designating a control store holding a plurality of indicators and a destination field holding information on a branch target address. The method comprises determining from the opcode field whether or not the test will check the state of one indicator or a plurality of indicators in the designated control store, accessing the designated control store to check the state of said one or said plurality of indicators depending on the determination, and generating a branch target address using information in the destination field in dependence on the state of the or each indicator checked.

Abstract: An M-bit folding/interpolating analog-to-digital converter (ADC) circuit, comprising a reference voltage generator, a converter, an interpolator, an amplifying stage, a comparator, and an encoder. The converter has an amplifier that receives at least one of a plurality of first reference voltage signals and outputs a plurality of coarse bits. The converter also has N-number of folding blocks, which output a plurality of folded signals. Each folding block comprises a plurality of capacitors, a differential amplifier and a feedback element. The folded signals output by the converter are then interpolated, amplified, compared and output as a plurality of fine bits. The encoder receives the coarse and fine bits and outputs the digital signal.

Abstract: An architecture and a method for a cryptography acceleration is disclosed that allows significant performance improvements without the use of external memory. Specifically, the chip architecture enables “cell-based” processing of random-length IP packets. The IP packets, which may be of variable and unknown size, are split into fixed-size “cells.” The fixed-sized cells are then processed and reassembled into packets. The cell-based packet processing architecture of the present invention allows the implementation of a processing pipeline that has known processing throughput and timing characteristics, thus making it possible to fetch and process the cells in a predictable time frame. The architecture is scalable and is also independent of the type of cryptography performed. The cells may be fetched ahead of time (pre-fetched) and the pipeline may be staged in such a manner that attached (local) memory is not required to store packet data or control parameters.

Abstract: A method for setting indicators in a control store of a computer system for conditionally performing operations, comprises providing a control store setting instruction defining an execution condition and specifying a control store to be set according to the condition, specifying in the instruction an operand lane size over which a setting operation is to be performed, the operand lane size specified being selected from a plurality of predetermined operand lane sizes, performing the setting operation defined in the setting instruction on a per operand lane basis over a plurality of operand lanes, writing the result of the setting operation to the control store specified in the instruction to set a plurality of indicators on a lane by lane basis, wherein one or a predetermined plurality of indicators is set for each operand lane in dependence on the size of the operand lane defined in the instruction. An instruction for performing the preferred method is also disclosed.

Abstract: Digital data signals at a variable input frequency are converted by a numerically controlled oscillator and an interpolator to a signal at a fixed output sampling frequency. The conversion of the variable input frequency to the fixed output sampling frequency may be by a factor other than an integer. The interpolated digital data signals at the fixed output sampling frequency are then modulated into a pair of trigonometric signals at a programmable carrier frequency, one signal having a cosine function and the other signal having a sine function. The modulated signals at the fixed output sampling frequency are then combined to create a modulated signal at a carrier frequency determined by the frequency of the sine and cosine signals. The modulated signal is sampled at the fixed output sampling frequency and converted to a corresponding analog signal using a digital-to-analog converter.

Abstract: The present invention provides a system and method for performing ranging operations in a cable modem system. In accordance with embodiments of the present invention, transmission times, transmission power levels, transmission carrier frequencies, and pre-equalization parameters are adjusted to provide for robust operation of the cable modem system. More particularly, iterative processing steps are used to provide coefficient ordering, scaling, and aligning between the multiple cable modems and the cable modem termination system present in a cable modem system.

Abstract: Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C3MOS) logic fabricated in conventional CMOS process technology. An entire family of logic elements including inverter/buffers, level shifters, NAND, NOR, XOR gates, latches, flip-flops and the like are implemented using C3MOS techniques. Optimum balance between power consumption and speed for each circuit application is achieve by combining high speed C3MOS logic with low power conventional CMOS logic. The combined C3MOS/CMOS logic allows greater integration of circuits such as high speed transceivers used in fiber optic communication systems. The C3MOS structure enables the use of a power supply voltage that may be larger than the voltage required by the CMOS fabrication process, further enhancing the performance of the circuit.

Abstract: An integrated circuit formed on a semiconductor chip, comprising a low pass filter circuit having a first resistor of a first resistance value and a capacitor of a first capacitance value, wherein the first resistance value and the first capacitance value determine a comer frequency of the filter; and a tuning circuit having a second resistor of a second resistance value, a switched-capacitor of a third resistance value and a comparator that compares two voltage signals to produce a control signal, wherein the control signal adjusts the first and second resistance values as a function of the third resistance value. The corner frequency of the filter can be adjusted by varying one or more reference voltage signals. In combination, the comer frequency of the filter is adjusted by changing the frequency of a clock that controls the switched-capacitor to decrease the circuit sensitivity.

Abstract: A system and method of creating a highly efficient digital amplifier which can take either analog or digital inputs, and produce a high power accurate representation of the input to drive speakers or other low impedance load is described. The system employs a transition detector and delay unit which allows the comparator of the signal modulator to ignore its inputs for a pre-determined number of subsequent clock cycles once an output transition has been detected. Through the use of faster clocks and variable clock cycle skips upon the comparator's output transition, finer resolution of the feedback's clock period for noise-shaping purposes is achieved. Finer resolution of the clock period allows the present invention to employ a more aggressive noise-shaping than previously possible.

Abstract: A Class AB voltage-to-current converter includes a primary transconductance stage, secondary transconductance stage, and a biasing circuit. The biasing circuit generates a primary bias voltage that is greater than a generated secondary bias voltage. As such, the primary transconductance stage 12 becomes active before the secondary transconductance stage 14 with respect to the magnitude of a differential input voltage 18, thereby allowing the transconductance of the secondary transconductance stage to be added (or subtracted) from the transconductance of the primary stage to improve the overall transconductance of the Class AB voltage-to-current convert.

Abstract: A method and apparatus for providing local control of processing elements in a network of multiple context processing element are provided. A multiple context processing element is configured to store a number of configuration memory contexts. This multiple context processing element maintains data of a current configuration. State information is received from at least one other multiple context processing element. At least one configuration control signal is generated in responses to the state information and the data of a current configuration. One of multiple configuration memory contexts is selected in response to the configuration control signal, the selected configuration memory context controlling the multiple context processing element. Each multiple context processing element in the networked array of multiple context processing elements has an assigned physical and virtual identification.

Abstract: A system and method is provided for interleaving data in a communication device. The system includes a memory that stores blocks of data to be interleaved. In addition to the memory, the system includes a write module and a read module, each of which is coupled to the memory. The write module is configured to receive a burst of data and write blocks of data from the burst into the memory. The write module is also configured to provide control information to the read logic. The control information includes a rolling burst counter and a burst profile bank identifier for each block. If interleaving is activated, the control information also includes information pertaining to how the read module should interleave the block. If interleaving is not activated, the control information also includes the byte length size of the burst. The read module reads blocks of data from memory in either an interleaved fashion or a non-interleaved fashion in accordance with the control information.

Abstract: A sense amplifier having a sampling circuit to sample the amplifier input signal; a reference node storing a reference signal corresponding to the input signal; and a timing circuit activating the sampling circuit for a predetermined interval, and admitting the reference signal to the reference node. The sense amplifier also can include a pump capacitor substantially maintaining a value of the reference signal; and a gain circuit coupled with the reference node and disposed to adaptively adjust gain of an output signal produced by the sense amplifier. The sense amplifier can be a single-ended sense amplifier.

Abstract: Improved carrier recovery, symbol timing, and carrier phase tracking systems and methods suitable for use in connection with a dual-mode QAM/VSB receiver system are disclosed. Carrier and phase recovery systems operate on complex signals representing symbols having the same time stamp for each phase error term. in-phase signals are sampled twice a symbol at the in-phase symbol sampling time and at the quadrature-phase symbol sampling time. The signals are de-multiplexed to generate I and XI data streams, where I represents the in-phase sampling time signals and XI represents mid-symbol point sample times. A similar procedure is carrier out on quadrature-phase signals. When the in-phase signal is de-multiplexed to generate a symbol I, the quadrature-phase signal is de-multiplexed to generate its mid-symbol point XQ. Both I and Q are decoded in a decision device to define a symbol error term, which is combined with the opposite mid-symbol signal to define a phase error term PI and PQ for each rail.

Abstract: A memory controller may include a request queue for receiving transaction information (e.g. the address of the transaction) and a channel control circuit. A control circuit for the request queue may issue addresses from the request queue to the channel control circuit out of order, and thus the memory operations may be completed out of order. The request queue may shift entries corresponding to transactions younger than a completing transaction to delete the completing transaction's information from the request queue. However, a data buffer for storing the data corresponding to transactions may not be shifted. Each queue entry in the request queue may store a data buffer pointer indicative of the data buffer entry assigned to the corresponding transaction. The data buffer pointer may be used to communicate between the channel control circuit, the request queue, and the control circuit. In one implementation, the request queue may implement associative comparisons of information in each queue entry (e.g.

Abstract: Provided is an architecture (hardware implementation) for an authentication engine to increase the speed at which SHA1 multi-loop and/or multi-round authentication algorithms may be performed on data packets transmitted over a computer network. As described in this application, the invention has particular application to the variant of the SHA1 authentication algorithms specified by the IPSec cryptography standard. In accordance with the IPSec standard, the invention may be used in conjunction with data encryption/encryption architecture and protocols. However it is also suitable for use in conjunction with other non-IPSec cryptography algorithms, and for applications in which encryption/decryption is not conducted (in IPSec or not) and where it is purely authentication that is accelerated. Among other advantages, an authentication engine in accordance with the present invention provides improved performance with regard to the processing of short data packets.

Abstract: A modem and method for operating same. A receiver circuit of the modem is coupled to receive a continuous analog signal from a communication channel. This analog signal includes both packet and idle information. The receiver circuit monitors the analog signal to detect the presence of idle information. Upon detecting idle information, the receiver circuit enters a standby mode in which the processing requirements of the receiver circuit are reduced. A burst mode protocol is also provided, in which packets of digital information are modulated by a transmitter circuit 6f the modem, thereby converting the packets of digital information into analog signal bursts of discrete duration. These analog signal bursts are transmitted from the transmitter circuit to a telephone line. However, the transmitter circuit does not generate any signals between the analog signal bursts. A receiver circuit monitors the telephone line to detect the analog signal bursts.

Abstract: A resonant oscillator circuit includes an active device and a resonator that causes the active device to oscillate at a resonant frequency of the resonator. The active device includes one or more transistors that are DC biased using one or more resistors. The bias resistors generate thermal noise that is proportional to the resistance value. An external inductor circuit is connected across the output terminals of the active device and in parallel with the resonator. The external inductor circuit shorts-out at least some of the thermal noise that is generated by the bias resistors, and thereby reduces the overall phase noise of the resonant oscillator.