Abstract: A method for dynamically regulating the power consumption of a high-speed integrated circuit which includes a multiplicity of processing blocks. A first metric and a second metric, which are respectively related to a first performance parameter and a second performance parameter of the integrated circuit, are defined. The first metric is set at a pre-defined value. Selected blocks of the multiplicity of processing blocks are disabled in accordance with a set of pre-determined patterns. The second metric is evaluated, while the disabling operation is being performed, to generate a range of values of the second metric. Each of the values corresponds to the pre-defined value of the first metric. A most desirable value of the second metric is determined from the range of values and is matched to a corresponding pre-determined pattern. The integrated circuit is subsequently operated with selected processing blocks disabled in accordance with the matching pre-determined pattern.

Abstract: Circuitry to remove switches from signal paths in integrated circuit programmable gain attenuators. Programmable gain attenuators and programmable gain amplifiers commonly switch between signal levels using semi-conductors switches. Such switches may introduce non-linearities in the signal. By isolating the switches from the signal path linearity of the PGA can be improved.

Abstract: The present invention provides for a system for operating a communication device (20) for reception of scheduled intermittent information messages (22) with a dual mode timer (70) that extends battery life. A controller (50) schedules the timer (70) to power down all idle components of the device (20) between message receptions in a power saving sleep mode to conserve battery power. During active mode when the device is fully active in reception of messages, the timer (70) uses a reference oscillator (90) with a relatively high frequency to support digital processing by the receiver (26). During sleep mode when only the timer is powered on, a much lower frequency sleep oscillator (96) is used to maintain the lowest possible level of power consumption within the timer itself. The timer (70) has provision for automatic temperature calibration to compensate for timing inaccuracies inherent to the low-power low-frequency crystal oscillator (96) used for the sleep mode.

Abstract: A method and system for combing requests for data bandwidth by a data provider for transmission of data over an asynchronous communication medium is provided. A headend receives one or more bandwidths requests from one or more cable modems via upstream communication. A scheduler then combines one or more bandwidths requests from the same cable modem to create a single data burst bandwidth. The headend then grants the data burst bandwidth to the appropriate cable modem via downstream communication.

Abstract: Classification of packets into flows is an inherent operation performed by networks that support enhanced services. To support multiple-dimensional packet classification, a packet classification system is provided to select representative bits from a packet to look up a set of rules. The per-flow classification works with a large set of rules, where each rule comprises of multiple fields and also allows fast dynamic variation in the rule set. A lookup process includes a simple and finite set of instructions that can be efficiently implemented as pipelined hardware and support very high packet arrival rates.

Abstract: A graphics integrated circuit chip is used in a set-top box for controlling a television display. The graphics chip processes analog video input, digital video input, a graphics input and an audio input simultaneously. The chip includes a display engine that processes graphics images organized as windows. The display engine processes graphics images formatted in any one of a plurality of formats including a color look up table (CLUT) format. A color look-up (CLUT) table loading mechanism preferably facilitates the transfer of real-time CLUT table data during graphics composition. The loading mechanism may be triggered by a window descriptor that contains a color look-up table load command.

Abstract: A communication line having a plurality of twisted wire pairs connects a plurality of transmitters, one transmitter at each end of each twisted wire pair, with a plurality of receivers, one receiver at each end of each twisted wire pair. Each receiver receives a combination signal including a direct signal from the transmitter at the opposite end of the twisted wire pair with which the receiver is associated and a plurality of far-end crosstalk (FEXT) impairment signals, one from each of the remaining transmitters at the opposite end of the communications line. A plurality of FEXT cancellation systems, one associated with each receiver, provides a replica FEXT impairment signal. A device associated with each receiver is responsive to the combination signal received by the receiver and the replica FEXT impairment signal provided by the FEXT cancellation system associated with the receiver for substantially removing the FEXT impairment signals from the combination signal.

Abstract: The present invention provides for a system and method for improvement of radio transmitter and receiver frequency accuracy for a local radio communication unit that communicates digital data with a remote communication unit. In the local unit the received radio signal is down-converted, and converted to complex baseband digital samples by an analog-to-digital converter. A downlink digital phase rotator applies a fine frequency shift to the samples in accordance with a receiver frequency offset command. The resultant baseband signal is used by the data demodulator and by a receiver frequency error estimator to obtain receiver frequency errors. A data modulator generates baseband complex samples which are shifted in carrier frequency by an integrated uplink digital phase rotator in accordance with a transmitter frequency offset command. The modulated samples are then converted by a digital-to-analog converter and upconverted in frequency for radio transmission to the remote unit.

Abstract: A method and system for processing packets allows consolidation of security processing. Security processing is performed in accordance with multiple security policies. This processing is done in a single front end processing block. Different security processes can be performed in parallel. Processing overhead is reduced by eliminating the need to redundantly check packet characteristics to assess the different security requirements imposed by security policies. Further, the present invention also substantially reduces the CPU cycles required to transport data back and forth from memory to a cryptographic coprocessor.

Abstract: A communications network switch includes a plurality of network ports for transmitting and receiving packets to and from network nodes via network links, each of the packets having a destination address and a source address, the switch being operative to communicate with at least one trunking network device via at least one trunk formed by a plurality of aggregated network links. The communications network switch provides a method and apparatus for balancing the loading of aggregated network links of the trunk, thereby increasing the data transmission rate through the trunk.

Abstract: A method for reducing a propagation delay of a digital filter. The digital filter has an input path and an output path and includes a set of delay elements and a number of taps. The taps couples the input path to the output path. Each of the taps includes a coefficient, a multiplier and an adder. Each of the delay elements is disposed between two adjacent taps. The delay elements are placed in both the input path and the output path of the digital filter, such that the digital filter has fewer delay elements in the input path than a direct-form digital filter having the same number of taps in a direct-form structure and has fewer delay elements in the output path than a transposed-form digital filter having the same number of taps in a transposed-form structure, and such that the digital filter has same transfer function as the direct-form digital filter and the transposed-form digital filter.

Abstract: Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages; a first stage compensates ISI components induced by characteristics of a transmitter's partial response pulse shaping filter in a demodulator, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel in a Viterbi decoder. High speed decoding is accomplished by reducing the DFE depth by providing an input signal from a multiple decision feedback equalizer to the Viterbi based on a tail value and a subset of coefficient values received from a unit depth decision-feedback equalizer. Power reduction is accomplished by adaptively truncating active taps in the NEXT, FEXT and echo cancellation filters, or by disabling decoder circuitry portions, as channel response characteristics allow.

Abstract: Digital signals provided by a repeater connected to a plurality of clients by unshielded twisted wire pairs, are converted to analog signals which become degraded during transmission through the wires. Clients convert the degraded analog signals to digital signals. Digital signal phases are coarsely adjusted to have assumed zero crossing times coincide in-time with a clock signal zero crossing. Signal polarity, and the polarity of any change, is determined at the assumed zero crossing times of the digital signals. Pre-cursor and post-cursor responses, resulting from signal degradation, are respectively inhibited by a feed forward and a decision feedback equalizer. The time duration of post-cursor response is further inhibited by a high pass filter and a tail canceller. Phase adjustments are made, after response inhibition, by determining the polarity, and the polarity of any change, at the assumed zero crossing times.

Abstract: A system and method for a generalized packet header suppression mechanism is described. This mechanism is implemented via a descriptor table. An exact copy of the descriptor table is stored in both the sender and receiver of packets via a communication medium. Entries in the descriptor table provide the information necessary to both suppress and expand the headers of well-known packets. The sender of the packet uses the descriptor table to suppress the packet header prior to transmitting the packet over the communication medium. When the packet reaches the receiver, the receiver uses the descriptor table to expand or reconstruct the packet header. This procedure results in less bandwidth required to transmit well-known messages because known header data is not transmitted via the medium, thereby not wasting bandwidth. The suppression mechanism allows the complete suppression of the header of a packet (as opposed to the traditional payload suppression) by a shorter message descriptor.

Abstract: A resonant oscillator circuit includes an active device and a resonator that causes the active device to oscillate at a resonant frequency of the resonator. The active device includes one or more transistors that are DC biased using one or more resistors. The bias resistors generate thermal noise that is proportional to the resistance value. An external inductor circuit is connected across the output terminals of the active device and in parallel with the resonator. The external inductor circuit shorts-out at least some of the thermal noise that is generated by the bias resistors, and thereby reduces the overall phase noise of the resonant oscillator.

Abstract: A method for controlling a flow of packet data in a memory management unit of a network switch fabric is disclosed. A first portion of a data packet is received at a port on an ingress bus ring of the network switch fabric. A class of service for the data packet is determined based on the first portion and the portion is stored in a packer RAM of the port based on the class of service. Subsequent portions of the data packet are stored in the packer RAM. Once the predetermined number of portions have been received, the predetermined number of portions is sent to a packet pool RAM. A reference pointer to a first predetermined number of portions is sent to a transaction queue once an end of packet is detected and an egress scheduler detects a presence of a ready packet in the transaction queue and notifies an unpacker of the ready packet. The unpacker puts the ready packet into a FIFO and the ready packet is sent to an ingress/egress module.

Abstract: A gain compensator compensates for the gain variation of a varactor-tuned voltage tuned oscillator (VCO) in a phase lock loop (PLL). The VCO includes a parallel LC circuit having multiple fixed capacitors that can be switched-in or switched-out of the LC circuit according to a capacitor control signal to perform band-select tuning of the VCO. The gain compensator compensates for the variable VCO gain by generating a charge pump reference current that is based on the same capacitor control signal that controls the fixed capacitors in the LC circuit. The gain compensator generates the charge pump reference current by replicating a reference scale current using unit current sources. The number of times the reference scale current is replicated is based on the fixed capacitance that is switched-in to the LC circuit and therefore the frequency band of the PLL.

Abstract: Improved carrier recovery and symbol timing systems and methods suitable for use in connection with a dual-mode QAM/VSB receiver system is disclosed. Carrier and symbol timing acquisition and tracking loops are phase/frequency locked to an inserted pilot signal provided in an input VSB spectrum at a given frequency. An input spectrum is centered about baseband and the pilot is extracted by an equivalent filter which functions as a bandpass filter having pass bands centered about the pilot frequency. Since the pilot signal's frequency is given, its position in the frequency domain for any sampling frequency, is deterministic. The receiver's sampling frequency is provided such that the relationship is expressed as fc=fs/4. When tracked by a phase-lock loop, the pilot signal will appear at the correct location in the spectrum if the sampling frequency fs is correct, and will be shifted in one direction or the other if the sampling frequency fs is too high or too low.

Abstract: A method and apparatus for providing local control of processing elements in a network of multiple context processing element are provided. A multiple context processing element is configured to store a number of configuration memory contexts. This multiple context processing element maintains data of a current configuration. State information is received from at least one other multiple context processing element. At least one configuration control signal is generated in response to the state information and the data of a current configuration. One of multiple configuration memory contexts is selected in response to the configuration control signal, the selected configuration memory context controlling the multiple context processing element. Each multiple context processing element in the networked array of multiple context processing elements has an assigned physical and virtual identification.

Abstract: A decode circuit for selecting one of a plurality of output lines in dependence on the status of a plurality of input lines, the circuit comprising: a first decode arrangement comprising: a first decode node; first precharging circuitry for charging the first decode node to a charging potential; first discharging circuitry comprising a plurality of switching means each operable in dependence on the status of a respective one of the input lines to couple the first decode node to a discharging potential, and first selection circuitry coupled to a respective one of the output lines and operable in response to a first enable signal to select that output line if the first decode node has not discharged; and a second decode arrangement comprising: a second decode node; second precharging circuitry for charging the second decode node to a charging potential; second discharging circuitry comprising a plurality of switching means each operable in dependence on the status of a respective one of the input lines to coupl