Patents Assigned to Cadence Design Systems, Inc.
  • Polar decoder processor
    Patent number: 11063614
    Abstract: In some examples, a polar decoder for implementing polar decoding of a codeword can be configured to implement alogarithmic likelihood ratio (LLR), an even bit, and an odd bit buffer, respectively. The polar decoder can be configured to employ a list-to-buffer mapping state register for the LLR buffer for loading LLR values for each path at a given stage of a decoding graph. The polar decoder can be configured to update and store LLR values for each path at the given stage. The polar decoder can be configured to employ a list-to-buffer mapping state register for the even bit buffer for loading even bit values from the even bit buffer and loading odd bit values from the odd bit buffer, and updating even or odd bit values for each path at the given stage of the decoding graph.
    Type: Grant
    Filed: November 21, 2019
    Date of Patent: July 13, 2021
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Rong Chen, Poojan Rajeshbhai Shah, Dan Nicolaescu
  • Input-directed constrained random simulation
    Patent number: 11055460
    Abstract: A system and method for input-directed constrained random simulation includes obtaining an initial state for a finite state machine (FSM) that models an electronic circuit design under test (DUT), the initial state assigning values to registers of the device under test, by providing an initial state function I(s) relating to the FSM to a satisfiability problem (SAT) solver to obtain register values that satisfy the initial state function. A random Boolean circuit R(i) is constructed. A SAT solver is queried for a satisfying assignment for a conjoined expression providing the conjunction of at least a valid-transition Boolean circuit T(s, i, s?) and the random Boolean circuit R(i), the valid-transition Boolean circuit describing valid transitions of the FSM as a function of current state s, inputs i, and next state s?. The satisfying assignment is added to the end of a constructed trace.
    Type: Grant
    Filed: May 21, 2020
    Date of Patent: July 6, 2021
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Ali Abdi, Guy Eliezer Wolfovitz
  • System, method and computer program product for automatic generation of sizing constraints by reusing existing electronic designs
    Patent number: 11048852
    Abstract: The present disclosure relates to a computer-implemented method for electronic circuit design. Embodiments may include receiving, using at least one processor, data corresponding to an electronic design schematic. Embodiments may further include analyzing the data to learn one or more device size parameters, a range of parameters, or a matching relationship of parameters based upon, at least in part, the electronic design schematic or the electronic design layout, wherein analyzing occurs without user action.
    Type: Grant
    Filed: July 26, 2019
    Date of Patent: June 29, 2021
    Assignee: Cadence Design Systems, Inc.
    Inventors: Elias Lee Fallon, Wangyang Zhang, Sheng Qian
  • Dynamic netlist modification of compacted data arrays in an emulation system
    Patent number: 11048843
    Abstract: A compaction circuit in an emulation system may store in a data array emulation data that may be read in subsequent emulation steps. For each emulation step, the compaction circuit may receive keeptags from a local control store word of the emulation step and store portions of emulation data identified by the keeptags. The keeptags in the control store words may be inserted by a compiler based upon whether a corresponding read port of emulation processor reads the stored data in the subsequent steps. The compaction circuit may also translate the logical read address of the stored data to a physical read address in the shared data array. A dynamic modification engine may enable dynamic modification of netlists while using the compacted data array. In response to a request, the dynamic modification engine may modify one or more keeptags and update read addresses in the control store words.
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: June 29, 2021
    Assignee: Cadence Design Systems, Inc.
    Inventors: Mitchell G. Poplack, Yuhei Hayashi
  • Systems and methods for high-speed data transfer over a communication interface
    Patent number: 11042500
    Abstract: A SPI master may configure a set of hardware registers associated with a SPI client with a set of communication parameters. The SPI master may send a message to the SPI client. The SPI master may periodically ping the SPI client until the SPI master receives an acknowledgement message from the SPI client in response to the message from the SPI master. The SPI master may periodically ping the SPI client based upon the set of communication parameters. The SPI client may transmit the acknowledgement message to the SPI master based upon the set of communication parameters. The SPI master may receive the acknowledgement message from the SPI client. The SPI master may determine a status of a read operation or a write operation associated with the message based upon the acknowledgement message.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: June 22, 2021
    Assignee: Cadence Design Systems, Inc.
    Inventors: Xiaolei Guo, Mitchell Poplack
  • Dynamic width-space patterns for handling complex DRC rules
    Patent number: 11042684
    Abstract: Embodiments according to the present disclosure relate to physically implementing an integrated circuit design using track patterns while conforming to the requirements of complex color based track systems, and using information about instances that have been included in the design. According to some aspects, the present embodiments provide “Dynamic Width Space Patterns (DWSP)” which are WSPs that are modified dynamically in consideration of neighboring geometries such that shapes created or edited using WSPs are design rule compliant. Embodiments can include providing visual indicators in a display of a portion of a design that is being created or edited, as well as possibly other alerts, so as assist a designer in creating a design rule compliant integrated circuit design that is also subject to WSPs.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: June 22, 2021
    Assignee: Cadence Design Systems, Inc.
    Inventor: Sachin Srivastava
  • Method and apparatus to accelerate verification signoff by selective re-use of integrated coverage models
    Patent number: 11036906
    Abstract: In the context of electronic design automation and in particular coverage-driven verification, each of a number of integrated coverage models to be merged for coverage analysis are divided between a code coverage model and a functional coverage model. During a coverage model generation phase, new code coverage models or functional coverage models are created only if they are not already in a coverage model database repository; otherwise, they are copied. During a merging phase, code coverage models or functional coverage models are loaded only if they have not already been loaded. Signatures that can be based on checksums can be used to determine whether the models are unique or duplicates of those already created or loaded. Selectivity in the creation and re-use of the respective coverage models provides computational time savings in each of the creation and loading phases.
    Type: Grant
    Filed: January 24, 2020
    Date of Patent: June 15, 2021
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Praveen Kumar Chhabra, Devraj Goyal, Amit Kumar Tiwari, Manisha Singla
  • Track assignment by dynamic programming
    Patent number: 11030378
    Abstract: Various embodiments described herein provide for track assignment of wires of a network of a circuit design by dynamic programming. In particular, various embodiments use a dynamic programming process to determine a set of breaking points for a routing wire of a global-routed and layer-assigned circuit design, and to determine track assignments for each of the sub-wires (sub-routes) formed by applying the set of selected breaking points to the routing wire. This results in a set of track-assigned sub-wires (or track-assigned sub-routes), which various embodiments can connect together to generate a connected set of track-assigned sub-wires that can be used in place of the routing wire.
    Type: Grant
    Filed: June 17, 2020
    Date of Patent: June 8, 2021
    Assignee: Cadence Design Systems, Inc.
    Inventors: Yi-Xiao Ding, Mehmet Can Yildiz, Zhuo Li
  • Routing based on pin placement within routing blockage
    Patent number: 11030377
    Abstract: Various embodiments described herein provide for routing of wires of a network of a circuit design based on pin placement within a routing blockage. In particular, various embodiments provide a routing solution for a circuit design with zero blockage violation when there is no pin inside routing blockage of the circuit design, and uses a parameter (e.g., an adjustable parameter) that controls accuracy at which a routing process handles a pin (e.g., as placed by a placement stage) in routing blockage of the circuit design. For example, the parameter can control how much detour is acceptable when handling routing for a pin inside a routing blockage.
    Type: Grant
    Filed: June 8, 2020
    Date of Patent: June 8, 2021
    Assignee: Cadence Design Systems, Inc.
    Inventors: Wing-Kai Chow, Mehmet Can Yildiz
  • Methods, systems, and computer program product for characterizing an electronic design with a susceptibility window
    Patent number: 11023636
    Abstract: Disclosed are methods, systems, and articles of manufacture for characterizing an electronic design with a susceptibility window. These techniques identify a set of multiple aggressors in an electronic design and determine, at a susceptibility window module stored in memory and executing in conjunction with a microprocessor of a computing node, a susceptibility window for an internal node of a victim and a timing window for the set of multiple aggressors in the electronic design. These techniques further determine a subset having at least one aggressor using at least the susceptibility window of the victim and the timing window for the set of multiple aggressors, and determine whether a glitch in the electronic design causes a violation at the internal node of the electronic design based at least in part upon the timing window and the susceptibility.
    Type: Grant
    Filed: May 13, 2020
    Date of Patent: June 1, 2021
    Assignee: Cadence Design Systems, Inc.
    Inventors: Igor Keller, Ratnakar Goyal, Manuj Verma, Harmandeep Singh
  • Method and system for sequential equivalence checking
    Patent number: 11023357
    Abstract: A method for sequential equivalence checking (SEC) of two representations of an electronic design may include using a processor, automatically selecting a plurality of cutpoints in the two representations of the electronic design; using a processor, automatically executing a prove-from strategy on the plurality of cut point pairs to identify a failed cut point pair in the two electronic designs; and using the processor, automatically extending a trace corresponding to the identified failed cut point pair to identify a deeper failed cut point pair or a failed output pair in the two electronic designs.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: June 1, 2021
    Assignee: Cadence Design Systems, Inc.
    Inventors: Ayman Hanna, Karam Abdelkader, Doron Bustan, Habeeb Farah, Thiago Radicchi Roque, Felipe Althoff
  • Methods, systems, and computer program product for characterizing timing behavior of an electronic design with a derived current waveform
    Patent number: 11023640
    Abstract: Disclosed are methods, systems, and articles of manufacture for characterizing timing behavior of an electronic design with a derived current waveform. A set of inputs is determined from a set of electrical characteristics of an electronic design or a portion thereof. Moreover, A derived current waveform is determined at one or more modules stored in memory and executing in conjunction with a microprocessor of a computing node based at least in part upon the set of inputs. The electronic design or the portion thereof is characterized based at least in part upon the derived current waveform.
    Type: Grant
    Filed: May 13, 2020
    Date of Patent: June 1, 2021
    Assignee: Cadence Design Systems, Inc.
    Inventors: Igor Keller, Chirayu S. Amin, Omid Assare
  • Method, system, and product to efficiently route interconnections following a free form contour
    Patent number: 11023645
    Abstract: An approach is described for a method, system, and product for detection of contours for data pads of a device having a free form contour, clustering integrated circuit pads and data pads, performing any angle routing based on a contour angle, and performing resistance balancing. For example, data pads of a display device having one or more curved contours (e.g. data pads arranged on an arc) are identified. Corresponding data pads and integrated circuit pads are then grouped together for routing interconnections and subsequently routed using any angle routing instead of merely routing interconnections with turns having 90-degree or 45-degree angles. Finally, the routed interconnects may be further refined/modified to balance resistances of the interconnections.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: June 1, 2021
    Assignee: Cadence Design Systems, Inc.
    Inventors: Xavier Alasseur, Arnold Jean Marie Gustave Ginetti
  • Hybrid deferred assertion for circuit design
    Patent number: 11023637
    Abstract: A logic simulation electronic design automation (EDA) application, the logic can be configured to receive a circuit design of an integrated circuit (IC) chip, the circuit design comprising an imported module comprising a list of simple immediate assertions (SIAs) for the imported module, wherein the circuit design comprises a first power domain and a second power domain, wherein the first power domain controls a power state of the second power domain and the imported module is assigned to the second power domain. The logic simulation EDA application can be configured to convert, in response to user input, each SIA in the list of SIAs into a respective hybrid deferred assertion (HDA) to form a list of HDAs for the imported module and execute a simulation of the IC chip, and execution of the simulation can include execution of a plurality of time slots for a plurality of simulation cycles.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: June 1, 2021
    Assignee: Cadence Design Systems, Inc.
    Inventors: Amit Kohli, Sulabh Nangalia, Apurva Kalia, Yonghao Chen, Mickey Rodriguez, Abhishek Kanungo
  • Method, system, and computer program product for characterizing electromigration effects in an electronic design
    Patent number: 11017136
    Abstract: Disclosed are methods, systems, and articles of manufacture for characterizing electromigration effects in an electronic design. These techniques determine an electrical characteristic at a port of a portion of an electronic design and select a number of frequencies in the frequency domain for the electrical characteristic. Multiple electric currents through a circuit component in the portion may be determined at least by performing a number of analyses for the number of frequencies. An electromigration effect may be characterized for the circuit component by using at least the multiple electric currents.
    Type: Grant
    Filed: July 29, 2019
    Date of Patent: May 25, 2021
    Assignee: Cadence Design Systems, Inc.
    Inventor: Qingyu Lin
  • System and method for repeating a synchronized set of layout geometries
    Patent number: 11017145
    Abstract: Embodiments disclosed are directed to systems and methods for modifying an electronic circuit design. According to embodiments, the method includes generating a circuit element of an electronic circuit layout on a graphical user interface, and generating an array group including a plurality of circuit elements. Each cell of the array group includes the same circuit element, and the array group is generated such that a change in at least one attribute of the array group is applied to each circuit element of the plurality of circuit elements.
    Type: Grant
    Filed: December 4, 2019
    Date of Patent: May 25, 2021
    Assignee: Cadence Design Systems, Inc.
    Inventors: Ashwani Kumar Sanwal, Vandana Gupta, Devendra Deshpande
  • System, method, and computer program product for optimization in an electronic design
    Patent number: 11003825
    Abstract: The present disclosure relates to a computer-implemented method for electronic design is provided. Embodiments may include receiving, using at least one processor, an electronic design and determining an objective function associated with the electronic design. Embodiments may further include optimizing the objective function using Bayesian optimization and generating a best hyper-parameter setting based upon, at least in part, the Bayesian optimization.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: May 11, 2021
    Assignee: Cadence Design Systems, Inc.
    Inventors: Saleha Khatun, Sheng Qian, Wangyang Zhang, Elias Lee Fallon
  • Deterministic loop breaking in multi-mode multi-corner static timing analysis of integrated circuits
    Patent number: 11003821
    Abstract: The present embodiments relate to static timing analysis (STA) of circuits. The STA can be carried out concurrently for multiple-mode-multiple-corners (MMMC) for circuits including combinational loops. The STA includes determining hard breaking points in the loop associated with each single-mode-single-corner (SMSC) view. The STA also includes merging constraints of all SMSC views to generate a merged set of constraints. The STA includes running MMMC STA for the circuit based on the merged set of constraints. The STA also includes determining a soft breaking point for the loop in the MMMC view for timing propagation and settling. The STA maintains consistency of breaking points across SMSC and MMMC views.
    Type: Grant
    Filed: February 21, 2020
    Date of Patent: May 11, 2021
    Assignee: Cadence Design Systems, Inc.
    Inventors: Sri Harsha Pothukuchi, Amit Dhuria
  • Complexity optimization of trainable networks
    Patent number: 10997502
    Abstract: Some embodiments perform, in a multi-layer neural network in a computing device, optimization of the multi-layer neural network, for example by making a convolutional change with a first plurality of convolutional filters, or by making a connection change of a first plurality of convolutional filters. In other embodiments, electronic design automation (EDA) systems, methods, and computer-readable media are presented for adding such a multi-layer neural network into an integrated circuit (IC) design.
    Type: Grant
    Filed: April 13, 2017
    Date of Patent: May 4, 2021
    Assignee: Cadence Design Systems, Inc.
    Inventors: Raúl Alejandro Casas, Samer Lutfi Hijazi, Piyush Kaul, Rishi Kumar, Xuehong Mao, Christopher Rowen
  • System and method for multiple device diagnostics and failure grouping
    Patent number: 10996270
    Abstract: Systems and methods for multiple device diagnostics are disclosed herein. Exemplary embodiments provide for a multiple device diagnostic system having a plurality of electronic devices selected for diagnosis based on at least one selection criterion, a diagnosis engine in data communication with a failure database, and a diagnosis results database in data communication with the diagnosis engine. Embodiments further provide that the failure database contains grouped failure data from at least one previously diagnosed electronic device, that the wherein the processor diagnoses defects in one or more of the plurality of electronic devices using the grouped failure data, and that the processor outputs the diagnosis results to the diagnosis results database.
    Type: Grant
    Filed: September 11, 2018
    Date of Patent: May 4, 2021
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Sameer Chillarige, Joe Swenton, Anil Malik, Krishna Chakravadhanula