Abstract: This disclosure relates to slew rate boosting for communication interfaces. A circuit can include a driver circuit coupled to an output node and configured to provide a data signal to the output node based on an input signal. The data signal can a similar logical state as the input signal. The circuit can include a signal transition boosting circuit coupled to the output node and configured to provide a boosting signal to the output node based on the input signal and a charge pump delay adjustment signal. The charge pump delay adjustment signal can define an amount of time after which the boosting signal is provided to the output node. The boosting signal can be provided to the output node to signal boost the data signal for the amount of time defined by the charge pump delay adjustment signal to provide a boosted data signal at the output node.

Abstract: Embodiments described herein include an emulator system having a synchronization subsystem comprising devices, organized in logical hierarchy, controlling synchronization of a system clock and system components during emulation execution. The devices of the logical hierarchy communicate bi-directionally, communicating status indicators upwards and execution instructions downwards. A TCI is designated “master TCI” and others are designated “slave TCIs.” The master TCI asserts a RDY status that propagates upwards to a root node for a number cycles. The slave TCIs execute in “infinite run” and continually assert the RDY status upwards to the root device regardless of the cycle count. The root node detects each RDY status and propagates downwards a GO instruction to the master TCI and the slave TCIs. In this way, the TCIs execute until the master TCI de-asserts RDY status. The result is only the master TCI is manipulated to, for example, start/stop emulation or perform iterative execution.

Abstract: Systems and methods for IC chip design testing can include a hardware emulator, having circuitry to emulate functionalities of an integrated circuit chip design and a buffer, detecting an assertion failure event indicative of a failed assertion on one of the functionalities, and storing a message indicative of the assertion failure event in the buffer. The circuitry can transfer, asynchronously relative to execution of the hardware emulator, the message from the buffer to a software host device without halting the execution of the hardware emulator. The software host device can receive the message indicative of the assertion failure event, and execute, asynchronously relative to the execution of the hardware emulator, at least one fail action instruction associated with the assertion failure event.

Abstract: Embodiments disclosed herein describe systems and methods for tuning phases of interface clocks of ASICs in an emulation system for a low latency channel and to avoid read errors. During a bring-up time (e.g., powering up) of the emulation system, one or more training processors may execute a software application to iteratively tune the phases of the interface clocks such that data is written to the interface buffers prior to being read out. To mitigate the problem of higher latency, the training processors may execute software application to tune the clock phases such that there is a small time lag between the writes and reads. The training processors may set the time lag to account for factors such as memory setup and hold, clock skews, clock jitters, and the predicted margin required to account for future clock drift due to carrying operating conditions.

Abstract: Various embodiments provide for a data sampler with one or more capacitive digital-to-analog converters (DACs) for adjusting a threshold voltage range of the data sampler. According to some embodiments, two or more capacitive DACs can be used to set a threshold voltage for a data sampler and, by doing so, serve as a trigger mechanism for the data sampler.

Abstract: Various embodiments described herein provide for a receiver device that includes a processor, a non-linear equalizer, an accumulation register, and a plurality of co-processors. Each of the plurality of co-processors is operably coupled to the processor, the non-linear equalizer, and the accumulation register. Each of the plurality of co-processors can be configured to receive a configuration value from the processor, receive a data signal for processing from the non-linear equalizer, process the data signal based on the configuration value, and provide at least a portion of the processed data signal to the processor.

Abstract: Various embodiments provide for routing a circuit design based on adjusting a routing demand. More specifically, some embodiments implement routing demand smoothing of a grid cell, routing overflow spreading of a grid cell, or some combination of both prior to detailed routing of a circuit design, which can result in improved detailed routing over conventional routing techniques.

Abstract: An integrated circuit (IC) test engine extracts an input to output propagation delay for each cell instance of each of a plurality of cell types in an IC design from an SDF file for the IC design. The IC test engine extracts a node slack of each cell instance of each of the plurality of cell types of the IC design from a node slack report. The IC test engine also generates cell-aware test patterns for each cell instance of each cell type in the IC design to test a fabricated IC chip that is based on the IC design for defects corresponding to a subset of a plurality of candidate defects characterized in the plurality of fault rules files. Each cell-aware test pattern is configured to sensitize and propagate a transition along the longest possible path to test small delay defects in cell instances of the fabricated IC chip.

Abstract: An emulation processor may be configured to support emulating unknown binary logic based on non-arbitrariness of the unknown binary logic. For example, an unknown binary logic signal may take the finite binary values of 0 and 1. The circuitry in the emulation processor is configured to generate and propagate outputs based on the interactions of known input binary signals with the unknown input binary signals having non-arbitrary states. The emulation processor may support the both combinational and sequential operations associated with the unknown binary logic.

Abstract: Various embodiments provide a method or system that implements a two-tap decision feedback equalizer by applying a first tap and a second tap on a first symbol of a data signal, each of the first and second taps having a first and second polarity to generate a first corrected data symbol and a second corrected data symbol. The first corrected data symbol and the second corrected data symbol is provided to a comparator to select a data symbol. The output of the comparator is provided to a clock data recovery circuit along with a previous data symbol of the data signal preceding the first data symbol.

Abstract: Embodiments include herein are directed towards a method for dynamic voltage and frequency scaling (DVFS) based timing signoff associated with an electronic design environment. Embodiments may include receiving, using a processor, an electronic design and specifying, via a graphical user interface, a voltage sweep for each power net associated with the electronic design. Embodiments may further include specifying, via the graphical user interface, at least one voltage sweep to be excluded from analysis. Embodiments may also include automatically generating DVFS configurations based upon, at least in part, the voltage sweep for each power net and the at least one voltage sweep to be excluded from analysis.

Abstract: Embodiments include herein are directed towards a method for use in an electronic design environment is provided. Embodiments may include receiving, at a client electronic device, an image of an electronic circuit and storing an electronic circuit design file. Embodiments may further include identifying the electronic circuit design file based upon, at least in part, the image of the electronic circuit. Embodiments may also include displaying a graphical representation of the electronic circuit at a display screen associated with the client electronic device.

Abstract: A pseudorandom logic circuit may be embedded as a hardware within an emulation system, which may generate pseudorandom keephot instructions. A masking logic may mask out portions in each pseudorandom keephot instruction, which may change state elements during execution. A cluster of emulation processors may execute masked pseudorandom keephot instructions to consume power when not executing mission instructions. The cluster of emulation processors may run keephot cycles, during which the cluster of emulation processors may execute the pseudorandom keephot instructions causing the cluster of emulation processors to continue consuming a roughly constant amount of power, either at a same or different voltage level, but supposed outputs of the pseudorandom keephot instructions may have no impact upon inputs and outputs generated during mission cycles.

Abstract: Disclosed is an improved approach for implementing a three-dimensional integrated circuit design with mixed macro and standard cell placement. This approach concurrently places both the macros and standard cells of the 3D-IC design onto two or more stacked floorplan and optimize the instance locations by timing, density, wire length and floorplan constraint.

Abstract: A fault rules engine generates a plurality of fault rules files, each of the fault rules files is associated with a respective cell type of a plurality of cell types in an integrated circuit (IC) design. Each fault rules file includes data quantifying a nominal delay for a given two-cycle test pattern and data quantifying a delta delay for the given two-cycle test pattern corresponding to a given candidate defect of a plurality of candidate defects of a given cell type of the plurality of cell types in the IC design. An IC test engine extracts an input to output propagation delay for each cell instance from a standard delay format (SDF) file for the IC design and generates cell-aware test patterns for each cell instance of each cell type in the IC design based on the plurality of fault rules files and the extracted input to output propagation delays.

Abstract: A fault rules engine generates a plurality of fault rules files. Each of the fault rules files is associated with a respective cell type of a plurality of cell types in an integrated circuit (IC) design, and each fault rules file of the plurality of fault rules files can include data quantifying a nominal delay for a given two-cycle test pattern of a set of two-cycle test patterns and data quantifying a delta delay for the given two-cycle test pattern corresponding to a given candidate defect of a plurality of candidate defects for a given cell type in the IC design. An IC test engine generates cell-aware test patterns based on the plurality of fault rules files to test a fabricated IC chip that is based on the IC design for defects corresponding to a subset of the plurality of candidate defects characterized in the plurality of fault rules files.

Abstract: The present disclosure relates to a computer-implemented method for electronic design verification. Embodiments may include receiving an electronic design at a verification environment. Embodiments may also include performing a simulation of a portion of the electronic design in an X-propagation mode. Embodiments may further include determining whether the simulation is entering an element during a time range and determining whether a clock/reset associated with the element has an active X-edge. If the clock/reset has an active X-edge, embodiments may include preventing a recordation of coverage metrics during the time range.

Abstract: Embodiments disclosed herein describe systems, methods, and products for safety verification of an IC design. A computer executing an illustrative EDA tool may perform a static cone of influence (COI) analysis of a gate-level netlist of the IC design to determine whether faults injected at combinational logic at different COIs are safe or dangerous. The computer may leverage this determination to perform a register-transfer level (RTL) simulation by generating and injecting equivalent faults to sequential logic in the IC design. The computer may further flexibly allow RTL simulations under different assumptions based upon downstream observability of the faults injected to the sequential logic. Because, RTL simulations are significantly faster than the gate-level simulations, the computer may efficiently calculate DC of one or more safety mechanism in the IC design.

Abstract: A system for optimizing scan pipelining may include a processor and a memory. The processor may generate and insert, based on prior analysis of the physical layout of the circuit, an optimized number of pipeline stages between a first block and a second block in a hardware test design, a first scan chain including at least one pipeline stage of a head pipeline stage or a tail pipeline stage. The processor may insert a plurality of flip-flops into the first scan chain. The processor may determine at least one clock to be used for the at least one pipeline stage, using the plurality of flip-flops so as to eliminate the need of a lockup element between the at least one pipeline stage and the plurality of flip-flops. The processor may generate, based on the at least one clock, a second scan chain that connects the at least one pipeline stage and the plurality of flip-flops.

Abstract: An emulator system and a method for emulating functionalities of an integrated circuit design are disclosed. In one aspect, the system includes a plurality of verification components each comprising circuitry configured to perform transactions with at least another verification component. The system can include a plurality of proxies, each executing on a processor and corresponding to a respective one of the verification components. The system can include a switch that is communicatively coupled with the proxies, the switch dynamically configurable to, in a first time duration, operate with a first subset of the proxies to enable a first transaction between a functional module of the design and a first verification component. The switch can be dynamically configurable to, in a second time duration, operate with a second subset of the proxies to enable a second transaction between the functional module and a second verification component.