Abstract: Disclosed are methods, systems, and articles of manufacture for characterizing an electronic design with efficient cell cloning. A cell instance corresponding to multiple similar cell instances in a view of an electronic design may be identified, where the cell instance is instantiated from a master parameterized cell. An analysis engine may be configured at least by associating a parameter of the master parameterized cell with multiple different parameter values respectively corresponding to the multiple similar cell instances. An analysis result including respective metric values corresponding to the multiple similar cell instances may be generated at least by performing an analysis that sweeps across the multiple different parameter values.

Abstract: The present disclosure relates to a computer-implemented method for mixed signal design verification. Embodiments may include receiving, using a processor, an electronic circuit design and compiling and elaborating the electronic circuit design. Embodiments may also include simulating the electronic circuit design and updating, during the simulating, a System Verilog User-Defined Resolution function (“SV-UDR”) associated with the electronic circuit design.

Abstract: A high-speed multiplexor comprises a set of differential input pairs to receive and mix a set of differential input signals at a differential output node pair. The high-speed multiplexer further comprises an active inductive load pair driven by the input stage using the mixed set of differential input signals. Each active inductive load comprises a p-channel field effect transistor (pFET) device connected to one of the differential output node pairs and a resistor connected between a gate node and a drain node of the pFET device. The multiplexer further comprises a first cross-coupling capacitor connected between the gate node of a first inductive load and a second output node of the differential output node pair and a second cross-coupling capacitor connected between the gate node of a second inductive load and a first output node of the differential output node pair.

Abstract: Aspects of the present disclosure address systems and methods for clock tree synthesis (CTS). A first iteration of CTS is performed to generate an intermediate clock tree for an integrated circuit (IC) design that includes one or more macros. Target pin insertion delays (PIDs) for the one or more macros are computed based on the intermediate clock tree using a linear program. A second iteration of CTS is performed using the target PIDs for the one or more macros to generate an optimized clock tree for the IC design.

Abstract: The embodiments described herein provide for a method and system for training an optimal decision feedback equalization (DFE) coefficient for use in GDDR and DDR applications. The method includes determining a first expected bit pattern using a reference voltage. The method further includes determining a transition voltage value of the first expected bit pattern. The method further includes receiving a second expected bit pattern having a same first bit as the first expected bit pattern. The method further includes determining a transition voltage value of the second expected bit pattern using the reference voltage. The method further includes calculating an optimal reference voltage value by averaging the transition voltage values of the first expected bit pattern and the second-expected bit pattern and storing the optimal reference voltage value in a register corresponding to a logic value of the same first bit.

Abstract: Embodiments described herein provide for an emulation system that supports efficiently generating outgoing messages to a test bench. The emulation system transmits the outgoing messages to the test bench various busses and interfaces. The compiled virtual logic writes the outgoing messages into memories of the emulation chips for queuing, and notification messages associated with the queued outgoing messages. A traffic processor transfers from memories to the test bench using buses and interfaces. The traffic processor reads a notification message from memory to identify the storage location with a corresponding queued outgoing message. The traffic processor then transmits DMA requests to I/O components (e.g., DMA engines) to instruct the I/O components to transfer the queued outgoing message to the host device.

Abstract: A SPI master may configure a set of hardware registers associated with a SPI client with a set of communication parameters. The SPI master may send a message to the SPI client. The SPI master may periodically ping the SPI client until the SPI master receives an acknowledgement message from the SPI client in response to the message from the SPI master. The SPI master may periodically ping the SPI client based upon the set of communication parameters configured by the SPI master in the set of hardware registers. The SPI master may receive the acknowledgement message from the SPI client. The SPI master may determine a status of a read operation or a write operation associated with the message based upon the acknowledgement message.

Abstract: A circuit can include a non-inverter circuit configured to generate a first clock signal with a first logic state during a first period of time in response to an input clock signal having the first logic state, and with a second logic state during a second period of time in response to the input clock signal having the second logic state. The circuit can include an inverter circuit that can be configured to generate a second clock signal with the second logic state during the first period of time in response to the input clock signal having the first logic state, and with the second logic state during the second period of time in response to the input clock signal having the second logic state.

Abstract: The present disclosure relates to an apparatus and method for continuous time linear equalization. Embodiments include determining, using a decision feedback equalization (“DFE”) training block, a voltage value for one or more resistor values. Embodiments may further include determining, using the DFE training block, a voltage value for one or more capacitor values and identifying a voltage difference between the voltage value for one or more resistor values and the voltage value for one or more capacitor values. Embodiments may further include iteratively performing the determining of the voltage value and identifying of the voltage difference for each of the plurality of capacitor values until the voltage difference is at one or more minimum values to generate one or more optimal resistor and capacitor coefficients for a continuous time linear equalization filter.

Abstract: The present disclosure relates to a computer-implemented method for electronic design is provided. Embodiments may include receiving, using at least one processor, an electronic design having one or more unoptimized nets. Embodiments may further include applying a genetic algorithm to the electronic design, wherein the genetic algorithm includes a multi-stage routing analysis. A first stage analysis may apply a device-level global routing analysis, a second stage analysis may include an intra-row routing analysis, a third stage may include an inter-row routing analysis, and a fourth stage may include a post-routing optimization analysis. Embodiments may also include generating an optimized routing of the one or more unoptimized nets and displaying the optimized routing at a graphical user interface.

Abstract: The embodiments disclosed herein describe a switching ASIC that provides a dynamic single-bit routing and multiplexing function in an emulation system. The switching ASIC may receive a set of incoming data streams from a first set of emulation devices (e.g., emulation ASICs), disassemble each data stream to the constituent bits, dynamically multiplex the bits, reassemble the multiplexed bits into outgoing data streams, and transmit the outgoing data streams to a second set of emulation devices. Multiple statically scheduled selection tables (UCSWs), one for each output lane of the switching ASIC, drive the selection and routing of bits from input slots of various input lanes to the output slots of the output lane.

Abstract: Disclosed is an approach to implement multi-die concurrent placement, routing, and/or optimization across multiple dies. This permits the multiple dies to be modeled as a single 3D space. Instead of being limited to a 2D plane, a cell can be placed to the area of any of the dies without splitting the netlist beforehand.

Abstract: The present disclosure relates to a computer-implemented method for electronic design is provided. Embodiments may include receiving, using at least one processor, an electronic design schematic and an electronic design layout and analyzing, via machine learning, at least one schematic feature from a pair of devices associated with the electronic design schematic. Embodiments may further include determining, based, at least in part, upon the analyzing, whether the pair of devices should be grouped together.

Abstract: An approach is described for a method, system, and product, the approaching includes a multi-cloud orchestrator that manages interfacing with multiple cloud service providers on behalf of a user. In some embodiments, the multi-cloud orchestrator includes a client interface layer for each cloud provider supported where each supported cloud provider is associated with a set of management data for tracking transfers and a set of mapping data for scheduling sequences of commands to satisfy user requests. In some embodiments, the process is tightly coupled with an electronic design system and that client side and circuit verification and processing tools in cloud provider provided computing environments.

Abstract: The present disclosure relates to a method for use with an electronic design. Embodiments may include displaying, at a graphical user interface, at least a portion of the electronic design and receiving a selection of a subcircuit at a first position of the graphical user interface. In response to a user input, embodiments may include transitioning the subcircuit from the first position to a second position of the graphical user interface and determining one or more direct and indirect connections resulting from a potential placement at the second position. Embodiments may include determining an influence metric by applying an optimized connectivity rules definition upon the potential placement at the second position and the one or more direct and indirect connections. Embodiments may also include displaying feedback at the graphical user interface based upon, at least in part, the influence metric.

Abstract: In some examples, a receiver can include a sampler circuit that can be configured to process a data input signal corresponding to a current bit received at a receiver based on a capacitive weighted signal to compensate for distortion effects that a previously received bit at the receiver has on the data input signal. The receiver can include a capacitive coupling feedback circuit that can be configured to generate the capacitive weighted signal corresponding to a weighted detected bit of the previously received bit based on a capacitance of a subset of capacitors of a plurality of capacitors of the feedback circuit. The capacitive coupling feedback circuit can be configured to selectively control a number of capacitors of the plurality of capacitors that are connected in parallel corresponding to the subset of capacitors to control an amount of weight applied to the detected bit to generate the capacitive weighted signal.

Abstract: Embodiments include herein are directed towards a method for use in an electronic design environment is provided. Embodiments may include receiving, using a processor, an electronic design and providing, at a graphical user interface, an option to change an object associated with the electronic design. Embodiments may further include identifying a damage area associated with the electronic design, the damage area including an object therein. Embodiments may also include generating a polygon for the damage area and caching one or more voids located outside of the damage area. Embodiments may further include performing a cut and stamp operation on a portion of the electronic design associated with the damage area and populating, at the graphical user interface, a repaired damage area.

Abstract: Provided is an improved method, system, and computer program product to implement simulation for photonic devices. A composite, multi-domain simulation model is disclosed, with connected domain-specific representations that allow the use of the most relevant simulator technology for a given domain. The model has external connection points either expressed as actual ports or virtual ones, embodied by simulator API calls in the model.

Abstract: Disclosed are methods, systems, and articles of manufacture for implementing an electronic design with high-capacity design closure. A reduced netlist may be generated for an analysis view of an electronic design based at least in part upon logic of interest in the analysis view. A closure may be performed based at least in part upon a union netlist, wherein the union netlist is generated from the reduced netlist. The electronic design may then be implemented based at least in part upon a result of the closure task.

Abstract: A scan chain engine can determine a set number of EXTEST scan chains for the IP block and based on a predetermined maximum number of EXTEST wrapper cells per EXTEST scan chain. The scan chain engine iteratively executes partitioning on the IP block to generate a set of partitions. Each partition in the set of partitions has a number of EXTEST wrapper cells that does not exceed the maximum number of EXTEST wrapper cells per EXTEST scan chain. The scan chain engine selectively merges partitions of the set of partitions to form a set of populated partitions that each include an EXTEST wrapper cell. The number of partitions is equal to the set number of EXTEST scan chains for the IP block. The scan chain engine generates wire paths connecting EXTEST wrapper cells of each populated partition to construct the set number of EXTEST scan chains for the IP block.