Abstract: A method and apparatus for critical and false path verification takes all the potential false paths and captures the conditions that would make them true paths (or false paths) as a Boolean expression (net list), for the combinational logic only. The net list does not have to be at the gate level, but can be a simplified gate level representation because the verification process is only concerned with the logical behavior, not the actual structure. This allows the simulation to execute more quickly. Since the conditions are only captured between register elements, it can be formally proved whether or not the path can be exercised. If no register value can activate the path, then the analysis is done. Otherwise, a simulation is performed to determine whether the register values required to active the condition actually occur. If the Boolean condition can be satisfied, the simulation is performed on the sequential logic to justify those values.

Abstract: The present invention introduces several methods for implementing integrated circuits that use gridless non Manhattan routing to connect the integrated circuit components. In one embodiment, the non Manhattan routed integrated circuits are created by creating an initial route and then compacting the design down. In another embodiment, a gridless non Manhattan integrated circuits are implemented by adapting a gridless Manhattan routing system into a gridless non Manhattan routing system by rotating a plane of a tile based maze router.

Abstract: An output buffer includes an output stage that includes a transconductance device configured to drive a capacitive load, and a first capacitor coupled to an input of the transconductance device. A converter converts an input clock signal into a current that is provided to charge the first capacitor during a specified interval. The converter includes a feedback loop to adjust the current so as to produce a specified logic level at the specified interval. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

Abstract: A method for diagnosing failures within an integrated circuit where known diagnostic fault simulators are unable to detect failure mechanisms which do not conform to known failure models. Basic boolean equations are used to describe the internal nodes forming the logic. These equations are then evaluated by way of a good machine simulation to determine which of the equations are (most) true for failing test patterns and (most) false for passing patterns. At the end of the good machine simulation a score is calculated to determine the number of times (or percentage) for which the equation is true for failing patterns and false for passing patterns. The method is particularly effective for finding shorted nets pairs in which the failure mechanism does not fall within known models. The method described is instrumental in greatly reducing the time required for manual analysis of failure mechanisms not conforming to known models.

Abstract: From a circuit diagram, an electrically connected circuit diagram network is selected. From a layout representing the circuit diagram, an electrically connected layout network is selected that represents the circuit diagram network. A first electrical terminal connection of a first component is selected that connects the first component with the circuit diagram network or with the layout network. A second electrical terminal connection of a second component is selected that connects the component with the circuit diagram network or with the layout network. A first electrical moment is calculated for the transmission path of the layout. A second moment of the corresponding transmission path of the circuit diagram is calculated. A relationship between the first moment and the second moment is predetermined. A value of a resistor or a value of the capacitor of the circuit diagram is now modified in such a way that the relationship is satisfied.

Abstract: A method of testing an integrated circuit including component blocks of random logic in a manufacturing environment is disclosed. The method includes the steps of performing built-in self tests, at least in part to test memory and data paths of the integrated circuit, performing diagnostics tests, at least in part to test the component blocks of random logic individually, performing stress tests using test vectors, at least in part to test the component blocks of random logic collectively; and performing scan-based tests of the integrated circuit, at least in part to test for structural faults in the integrated circuit.

Abstract: Geometric objects, such as polygons, are defined in a multi-dimensional data space. The geometric objects are represented by data segments for processing in a computer. “N” dimensional hierarchical trees, or “ng” trees, are generated to organize the data segments into “outside child nodes” and “inside child nodes” in accordance with a discriminator value. The discriminator value is selected for each layer or discriminator dimension in the ng tree. For the ng tree, one of “n” sides of a polygon is selected as the discriminator value. To create the ng tree, data segments are designated as “outside child nodes” if a data segment is outside the plane defined by the discriminator value, and data segments are selected as “inside child nodes” if the data segment is inside the plane defined by the discriminator value.

Abstract: A method and apparatus for designing a circuit system, including selecting a plurality of pre-designed circuit blocks to be used to design the circuit system, collecting data reflecting the experience of the designer regarding the pre-designed circuit blocks, the designer's experience being adaptable to a processing method, accepting or rejecting a design of the circuit system in a manner based on the designer's experience data and acceptable degree of risk, upon acceptance, forming block specifications containing criteria and modified constraints for each of the circuit blocks, upon acceptance, forming block specifications for deploying the circuit blocks on a floor plan of a chip, as a system on a chip, in compliance with the criteria and modified constraints, and substantially without changing the selected circuit block and the processing method.

Abstract: A method and apparatus for designing a circuit system, including selecting a plurality of pre-designed circuit blocks to be used to design the circuit system, collecting data reflecting the experience of the designer regarding the pre-designed circuit blocks, the designer's experience being adaptable to a processing method, accepting or rejecting a design of the circuit system in a manner based on the designer's experience data and acceptable degree of risk, upon acceptance, forming block specifications containing criteria and modified constraints for each of the circuit blocks, upon acceptance, forming block specifications for deploying the circuit blocks on a floor plan of a chip, as a system on a chip, in compliance with the criteria and modified constraints, and substantially without changing the selected circuit block and the processing method.

Abstract: An exemplary system for measuring noise in a device comprises a CPU, a memory coupled to the CPU, an interface coupled to the CPU for providing instructions processed by the CPU, a control unit coupled to the interface for receiving the instructions, a preamplifier circuit coupled to the control unit for implementing the instructions, a power supply unit controlled by the control unit for providing power to the preamplifier circuit, and a device holder selectively attached to the preamplifier circuit. In an exemplary embodiment, the preamplifier circuit further comprises a plurality of filters, an amplifier circuit, a plurality of switches for switching the amplifier circuit between a voltage amplifier mode and a current amplifier mode, and a variable loading resistor.

Abstract: A method and apparatus for designing a circuit system, including selecting a plurality of pre-designed circuit blocks to be used to design the circuit system, collecting data reflecting the experience of the designer regarding the pre-designed circuit blocks, the designer's experience being adaptable to a processing method, accepting or rejecting a design of the circuit system in a manner based on the designer's experience data and acceptable degree of risk, upon acceptance, forming block specifications containing criteria and modified constraints for each of the circuit blocks, upon acceptance, forming block specifications for deploying the circuit blocks on a floor plan of a chip, as a system on a chip, in compliance with the criteria and modified constraints, and substantially without changing the selected circuit block and the processing method.

Abstract: A system and method for testing an integrated circuit including one or more circuit blocks, each containing an internal core, and a test access port connected to a set of boundary-scan cells includes a select register for receiving and holding the address of a circuit block to be accessed. One or more demultiplexers provide an interface between input test access port signals and the various individual circuit blocks, and one or more multiplexers provide an interface between the various individual circuit blocks and the output test access port signals. The address bits read into the select register act as the select signal(s) for the one or more demultiplexers and multiplexers, causing input test access port signals to be selectively routed to the circuit block having the appropriate address and causing output signals to be selected from the same circuit block as the output test access port signals.

Abstract: Some embodiments provide a method of pre-computing routes for nets in a region of an integrated circuit (“IC”) layout. The method initially defines a set of partitioning lines for partitioning the region into a plurality of sub-regions during a routing operation. For a particular set of potential sub-regions, the method then identifies a first set of routes based on a first wiring model and a second set of routes based on a second wiring model. Each identified set of routes traverses the particular set of potential sub-regions. The method then stores the identified routes.

Abstract: A system for using machine learning based upon Bayesian inference using a hybrid monte carlo method to create a model for performing integrated circuit layout extraction is disclosed. The system of the present invention has two main phases: model creation and model application. The model creation phase comprises creating one or more extraction models using machine-learning techniques. First, a complex extraction problem is decomposed into smaller simpler extraction problems. Then, each smaller extraction problem is then analyzed to identify a set of physical parameters that fully define the smaller extraction problem. Next, complex mathematical models are created using machine learning techniques for all of the smaller simpler extraction problems.

Abstract: The present invention presents techniques for considering whether the effects of cross-talk coupling and other noise exceed the noise tolerance of a circuit. One aspect of the present invention uses a set of parameters to represent this noise. An exemplary embodiment uses a triangle or trapezoidal approximation to a glitch based on a set of parameters: the peak voltage value, the width, the leading edge slope and the trailing edge slope. These values are then used as the input of a library to look up the corresponding noise tolerance parameter set values. In a variation, a set of formulae can provide the noise tolerance parameter set values. In an exemplary embodiment, the noise tolerance parameter set is taken to include the minimum peak value for the noise to be possibly harmful and the minimum width value for the noise to be possibly harmful.

Abstract: A method for testing memory cells for data retention faults is disclosed. A first logical value is stored in a first cell, and a second logical value is stored in a second cell of a memory device. The second cell shares the same column with the first cell. The bitlines associated with the first and second cells are prevented from being precharged before the second cell can be read. After the second cell has been read repeatedly, the first cell is read, and the bitlines associated with the first and second cells are precharged. At this point, a data retention fault is determined to have occurred if the first cell does not contain the first logical value.

Abstract: The invention is directed towards method and apparatus that consider diagonal wiring in placement. Some embodiments of the invention are placers that use diagonal lines in calculating the costs of potential placement configurations. For instance, some embodiments estimate the wirelength cost of a placement configuration by (1) identifying, for each net in a net list, a bounding box that encloses all the circuit elements of the net, (2) computing an attribute of each bounding box by using a line that can be completely or partially diagonal, and (3) computing the wirelength cost estimate based on the computed attributes. To estimate the wirelength cost of different placement configurations, other embodiments construct connection graphs that model the net interconnect topologies. These connection graphs can have edges that are completely or partially diagonal. Other embodiments use diagonal lines to measure congestion costs of potential placement configurations.

Abstract: A method and system for testing multiported memories, especially when one or more of the ports are not directly accessible without intervening logic. The method and system segregates the multiported memory into at least two portions which are then used for testing the one or more ports which are not directly accessible.

Abstract: Provided are a method, article of manufacture, and apparatus for estimating delays of networks. An automated design system comprises a computer configured to identify a critical path in a network, calculate a delay for the technology-mapped version of the network, calculate a delay for the technology-independent version of the network, calculate a scale factor from the technology-mapped and technology-independent delays, and apply the scale factor to all the delays in the technology-independent network.

Abstract: According to a custom physical design process for integrated circuits, a method is provided for creating layouts characterized by optimal-length chains for different types of MOS circuit designs, including mixed-signal MOS designs. A chaining engine having a device library and operating on a computer converts a circuit representation such as a netlist file into a layout file characterized by optimal-length chains. Such conversion may be accomplished in linear time. From a circuit representation, a bipartite graph is prepared. A starting node in the bipartite graph is selected according to enumerated Euler trail algorithm rules. A constraint greedy walk is conducted to generate layout chains, and is preferably repeated until the bipartite graph is exhausted of edges, at which point the resulting layouts are returned. A single optimal layout solution can be obtained without enumerating all the possible layout options, resulting in a considerable speed advantage over conventional techniques.