Abstract: Provided are a method, article of manufacture, and apparatus for estimating delays of networks. An automated design system comprises a computer configured to identify a critical path in a network, calculate a delay for the technology-mapped version of the network, calculate a delay for the technology-independent version of the network, calculate a scale factor from the technology-mapped and technology-independent delays, and apply the scale factor to all the delays in the technology-independent network.

Abstract: An automated design rule checking software system processes a physical layout file of a circuit design to derive a list of vias needing design rule checks for violations in metal end, enclosure and/or exposure design rules. The process involves selection of vias likely to cause design rule check problems, selection of vias that violate an enclosure design rule, selection of vias violate metal end design rules, and design rule checks on the selected vias. Potentially problematic vias may be identified by expanding the dimensions of existing vias by a first predetermined minimum distance, subtracting out the metal area, and identifying those vias with residual portions remaining as potentially problematic vias. Candidate vias for an enclosure design rule check may be identified by expanding the dimensions of potentially problematic vias by a second predetermined minimum distance, subtracting out the metal area, and identifying those vias with residual portions remaining as violating the enclosure design rules.

Abstract: Method and system for carrier recovery and estimation of Doppler shift from a signal source that is moving relative to a signal receiver. A pure carrier preamble for the received signal is processed through each of two stages of a linear predictor to obtain a successively more accurate estimation of a Doppler frequency offset for the carrier. The received signal is downconverted by each stage estimation of the Doppler frequency offset, and the downconverted signal is processed through a decision feedback phase locked loop to provide a signal in which substantially all of the Doppler offset and/or phase angle are identified and removed. The system has low complexity, is fast, and is accurate to within an estimated few tens of Hertz and will work with signals having relatively low signal-to-noise ratios. The invention is useful for receipt of signals from satellites in low earth orbits (LEOs) and other non-geosynchronous orbits, and wherever a transmitter and receiver are moving relative to each other.

Abstract: A database for storing chip design information comprises a plurality of parallel arrays for storing a particular class of information. The union of related entries commencing at a given array index across the one or more parallel arrays of a particular class forms a structure for a given instance within a class. Between classes, individual records in an array may cross-reference, through an array index, records in other arrays. The inherent sequential nature of records stored in the array may be used as linking information, thus avoiding the requirement of storing linking pointers in memory. Rather than storing all of the coordinate or spatial information for a given shape, only the offset information from the preceding shape may be stored, with the assumption that the second shape starts at the ending point of the first shape. Certain default values or characteristics for information within the array records can be assumed unless overridden by an indicator in the array record.

Abstract: The present invention introduces methods for implementing gridless non Manhattan architecture for integrated circuits. In one particular embodiment, an integrated circuit layout containing horizontal, vertical, and diagonal interconnect lines is first created. Next, the integrated circuit layout is then compacted. The compacting method first creates groups of horizontal and diagonal interconnect lines sorted by vertical position and groups of vertical and diagonal interconnect lines sorted by horizontal position. The two groups are then compacted in a manner that ensures that a minimum manufacturing line spacing requirement is satisfied.

Abstract: A method and system for matching a node of a combinatorial block with a library cell in a technology library using truth tables. A truth table representing the function of the node of the combinatorial block is generated. Similarly, a truth table representing the function of the library cell is generated. If the truth tables match, then the node of the combinatorial block can be tiled with the library cell. The two truth tables may match if the tables have the same number of inputs and the same signature. Also, the truth tables may match if the inputs to one truth table are permuted and/or inverted, or if the output of the truth table is inverted. These variations of the truth tables are compared to determine if the truth tables match.

Abstract: A method and system are disclosed for finding the best match from a target library of simple logic cells for a complex logic circuit conception. The inventive method is flexible and can be adapted to several cost functions or criteria. The inventive method finds the best children nodes for a match of simple gates (AND, OR, NAND, NOR). The method allows one to improve the overall area of the final design while respecting the time constrains. It also allows one to smartly speed up the tiler process as this process does not have to investigate exhaustive lists of possible children. Two preferred embodiments are disclosed. One such embodiment is designed to improve slack time and the other is designed to minimize required area.

Abstract: An automated method and system is disclosed to determine an Integrated Circuit (IC) package interconnect routing using a mathematical topological solution. A global topological routing solution is determined to provide singular ideal IC package routing solution. Topological Global Routing provides a mathematical abstraction of the problem that allows multiple optimizations to be performed prior to detailed routing. Preliminary disregard of electrical routing segment width and required clearance allows the global topological solution to be determined quickly. The global topological solution is used in conjunction with necessary design parameters to determine the optimal geometric routing solution. Guide points are determined using the geometric routing solution. A detail router uses the guide points as corners when performing the actual routing.

Abstract: Some embodiments of the invention are placers that use diagonal lines in calculating the cost of potential placement configurations. For instance, some embodiments estimate the wirelength cost of a placement configuration by (1) identifying, for each net list, a bounding box that encloses all the circuit elements of the net, (2) computing an attribute of each bounding box by using a line that can be completely or partially diagonal, and (3) computing the wirelength cost estimate based on the computed attributes. To estimate the wirelength cost of different placement configurations, other embodiments construct connection graphs that model the net interconnect topologies. These connection graphs can have edges that are completely or partially diagonal. Other embodiments use diagonal lines to measure congestion costs of potential placement configurations. For instance, some placers use diagonal lines as cut lines that divide the IC layout into regions.

Abstract: A behavioral model for mixed signal RF circuits. The model approximates non-linear filtering effects for base-band (i.e. suppressed carrier) end-to-end systems analysis. The new model, the K-model, is a linear MIMO (multi-input-multi-output) model with output radius corrected by a non-linear SISO (single-input-single output) model and output angle corrected by a non-linear rotation. The SISO model uses a multi-tanh structure to synthesize a non-linear filter. The multi-tanh structure simulates non-linear behavior by gently switching between transfer functions as the base-band input varies. For excursions well into the steady state non-linear region of operation the K-model simulates large-signal base-band transients to within about 10 percent of those simulated with detailed unsuppressed-carrier models.

Abstract: A Wireless bridge conjoins two previously incompatible technologies within a single device to leverage the strengths of each. The Wireless bridge marries the Personal Area Network (PAN) technology of Bluetooth as described in Bluetooth Specification Version 1.0B with the Wireless Local Area Network (WLAN) technology described in the IEEE802.11a specification to provide a wireless system level solution for peripheral devices to provide Internet service so interactions. The invention brings together in a single working device implementations of these technologies so they do not interfere or disrupt the operation of each other and instead provide a seamless transition of a Bluetooth connection to Wireless Local Area Network/Internet connection. From the Wireless Local Area Network perspective the inventive wireless bridge extension allows a Bluetooth-enabled device to roam from one Wireless Access Point (bridge) to the next without losing its back end connection.

Abstract: A multi-faceted design platform acts as a tool for front-end hardware IC designers who design complex core base System on Chip (SoC). The design platform uses a network such as the Internet to search and gain access to previously designed virtual core blocks. The design platform provides a means to select and transfer all relevant information regarding the selected virtual core blocks and allows the designer to immediately incorporate the virtual core block into the new SoC design. The design platform further generates the appropriate source code files for immediate use with a plurality of known verification tools to verify both the integration and connectivity of the virtual core blocks as well as the basic functionalities of the SoC design.

Abstract: An efficient method for determining the periodic steady state response of a circuit driven by a periodic signal, the method including the steps of 1) using a shooting method to form a non-linear system of equations for initial conditions of the circuit that directly result in the periodic steady state response; 2) solving the non-linear system via a Newton iterative method, where each iteration of the Newton method involves solution of a respective linear system of equations; and 3) for each iteration of the Newton method, solving the respective linear system of equations associated with the iteration of the Newton method via an iterative technique. The iterative technique may be a matrix-implicit application of a Krylov subspace technique, resulting in a computational cost that grows approximately in a linear fashion with the number of nodes in the circuit.

Abstract: A method and apparatus for designing a circuit system, including selecting a plurality of pre-designed circuit blocks to be used to design the circuit system, collecting data reflecting the experience of the designer regarding the pre-designed circuit blocks, the designer's experience being adaptable to a processing method, accepting or rejecting a design of the circuit system in a manner based on the designer's experience data and acceptable degree of risk, upon acceptance, forming block specifications containing criteria and modified constraints for each of the circuit blocks, upon acceptance, forming block specifications for deploying the circuit blocks on a floor plan of a chip, as a system on a chip, in compliance with the criteria and modified constraints, and substantially without changing the selected circuit block and the processing method.

Abstract: A system and method for performing a timing analysis on virtual component blocks or other circuit models is provided wherein functional information obtained from the circuit's control inputs and their useful combinations is used to improve accuracy. The control inputs and data inputs for a circuit block are identified. Each functionally meaningful or useful control input combination is applied to the circuit block, and the topological delay for the data inputs are determined only along the paths that are not blocked by the control inputs. The delays along paths that are blocked are ignored. The analysis is further augmented by determining the topological delay for all paths originating at control inputs, without regard to blocking of paths, so as to reduce the chance for possible underestimation of delays from the data inputs.

Abstract: A Wireless bridge conjoins two previously incompatible technologies within a single device to leverage the strengths of each. The Wireless bridge marries the Personal Area Network (PAN) technology of Bluetooth as described in Bluetooth Specification Version 1.0B with the Wireless Local Area Network (WLAN) technology described in the IEEE802.11aspecification to provide a wireless system level solution for peripheral devices to provide Internet service interactions. The invention brings together in a single working device implementations of these technologies so they do not interfere or disrupt the operation of each other and instead provide a seamless transition of a Bluetooth connection to Wireless Local Area Network/Internet connection. From the Wireless Local Area Network perspective the inventive wireless bridge extension allows a Bluetooth-enabled device to roam from one Wireless Access Point (bridge) to the next without losing its back end connection.

Abstract: A computer-implemented method abstracts the timing constraints for latches internal to a digital logic circuit, resulting in a clock characterization model. Timing information (such as propagation delays, set-up and hold requirements) for latches and combinational logic circuits contained in a digital logic circuit are received, as is a description of a class of clock scheme for clocking the circuit. Clock parameters are selected for the clock scheme class. The internal timing constraints for the digital logic circuit are expressed as timing constraint expressions which are a function of the clock parameters. The expressions are combined to define a region of feasible clock operation expressed in terms of the clock parameters.

Abstract: A method of testing an integrated circuit including component blocks of random logic in a manufacturing environment is disclosed. The method includes the steps of performing built-in self tests, at least in part to test memory and data paths of the integrated circuit, performing diagnostics tests, at least in part to test the component blocks of random logic individually, performing stress tests using test vectors, at least in part to test the component blocks of random logic collectively; and performing scan-based tests of the integrated circuit, at least in part to test for structural faults in the integrated circuit.

Abstract: A method for designing a circuit block includes the steps of selecting a plurality of pre-designed circuit blocks to be used to design the circuit system, at least one of said circuit blocks being programmable; collecting data reflecting the experience of the designer regarding the pre-designed circuit blocks, the designer's experience being adaptable to a processing method; accepting or rejecting a design of the circuit system in a manner based on the designer's experience data and acceptable degree of risk; upon acceptance, forming block specifications containing criteria and modified constraints for each of the circuit blocks (FEA); and, upon acceptance, forming block specifications for deploying the circuit blocks on a floor plan of a chip, in compliance with the criteria and modified constraints without changing the selected circuit block and the processing method.

Abstract: A method for estimating the position of a matched cell takes into account the interconnectivities of that cell, without relying on the location of cells connected to the matched cell. The new method is referred to as the Weighted Center of Mass of Covered method. In this method, weights are given to the various nodes which are part of the match. These weights are based on the number of connections between the nodes and child nodes of the match. The placment of the matched cell is based on the initial positions given to the nodes makeing up the match, and the weights calculated for those nodes.