Abstract: A method is provided to produce an integrated circuit layout design comprising: providing in non-transitory storage a pPar parent cell that includes one or more pPar instances and that specifies one or more corresponding input parameter values; producing a graphical representation on a computer display screen of a first schematic design that includes a pPar parent instance; instantiating in non-transitory storage a parameterized cell supermaster that corresponds to the pPar parent cell; determining whether a core layout cell is stored in non-transitory storage that corresponds to the parameterized cell supermaster and the one or more corresponding input parameter values; in response to determining that such a core layout cell is stored, filling a first parameterized cell submaster with an instance of the stored core layout cell; in response to determining that such a core layout cell is not stored, using program code associated with the parameterized cell supermaster to generate a core layout cell; and storin

Abstract: The present invention provides a method for calibrating a computational model of a lithography process by calculating a demerit function using an intensity measurement at a location of a wafer; and calibrating the lithography model or a mask making model by determining values of parameters of the computational model using the calculated demerit function. The method may also use a second demerit function that is defined by the sum of squares of differences between a simulated and measured critical dimensions of a feature on the wafer.

Abstract: In one embodiment, a method comprises creating a simulation model for a column of bit cells in a memory, simulating the simulation model to generate a result; and displaying the result for a user. Each of the bit cells in the column is coupled to a different wordline, and the simulation model comprises one or more linear elements in place of a nonlinear element in each bit cell that is coupled to an inactive wordline. The one or more linear elements approximate a behavior of the nonlinear element while the wordline is inactive. A computer accessible storage medium storing a simulator that implements the method is contemplated, and the simulator itself is also contemplated, in various embodiments.

Abstract: Embodiments of the invention provide system and methods for EDA tools. Specifically, some embodiments of the invention provide an input infrastructure for EDA tools that gathers pertinent information surrounding an input cursor's present locality (or neighborhood) and then analyzes the pertinent information in view of an issued command to automatically determine suitable targets or subsequent operations that a user of the EDA tool may want to select next.

Abstract: A method of testing an Integrated Circuit (IC) includes: loading a sequence of data into a chain of circuit elements that hold data values, where outputs of at least some circuit elements are connected to inputs of adjacent circuit elements so values move sequentially through the chain between a chain input for loading values and a chain output for unloading values, and a first circuit element includes a retention element for saving values during power variations related to the IC. The method further includes: saving a value from the data sequence in the retention element; and accessing the retention element for verifying an accuracy of the saved value from the data sequence.

Abstract: A method for detecting and reporting changes in functional features of a simulation model caused by a software revision is disclosed. In one aspect, the method is independent of simulation model architecture. One performs regression testing with a plurality of feature-specific modules. The feature-specific modules are configured to generate a first set of information with the simulation model and compare the first set of information to a second set of corresponding information from the simulation model. In the above-described testing, the first set of information postdates the software revision and the second set of information predates the software revision.

Abstract: A printed circuit board (PCB) block diagram tool for block diagram level editing of a PCB design abstracted from a PCB physical layout tool is disclosed. The PCB block diagram tool includes a plurality of interface objects, a plurality of block objects and interconnect lines. The plurality of interface objects represents interfaces between components. Each of the plurality of interface objects include a plurality of signal, power and ground signal lines without defined physical assignment to pin or pad. The plurality of block objects represents a plurality of physical objects in the PCB physical layout tool. The plurality of blocks are configured to accept the plurality of interface objects. Interconnect lines connect the plurality of interface objects between the plurality of block objects.

Abstract: An invention is provided for affording CopyBack data integrity in a non-volatile memory system. When the potential for moving data with a CopyBack command occurs, a counter corresponding to the data is examined. When the counter is below a predetermined limit, the counter is incremented and data from the block of data is moved using a CopyBack command. However, when the counter reaches the predetermined limit, the counter is reset and data from the block of data is moved to system memory and examined for errors. Once any errors are corrected, the data is transferred back to the non-volatile memory.

Abstract: An improved method, system, and computer program product for selecting components for an early stage electronic design is disclosed. A library of cells is modeled and is characterized by parameter combinations, where the cell modeling information is based upon ranking and scoring of the cells in the cell library. Based upon design specification information for an electronic design, the cell modeling data is used to select one or more representative cells for the early stage design based upon the list of ranked cells. The rankings provide an indication of the appropriateness of the selected cells for the early stage design. The pre-modeling of the cells provides high efficiency at run-time when there is a need to quickly select cells for the early stage design.

Abstract: Techniques are presented for accounting for parasitics in the automated design of integrated circuits. In one set of techniques, model values for parasitic models are received on a schematic environment from a user, the parasitic models are evaluated from the schematic using the received model values, the parasitic models are transferred to a layout environment, and the transferred parasitic models are evaluated on the layout environment. In other techniques, model values are received for parasitic models from a user, the parasitic models are evaluated on the layout environment, and the process then backannotates the parasitic models evaluated on the layout environment and corresponding parameter values to a schematic environment.

Abstract: A method is provided to coerce a wire type net in an integrated circuit design to become a wreal net in the design, comprising: running a wreal coercion process on a computer system including the acts of, identifying a wire type net that is connected to a wreal net in an integrated circuit design; and converting the identified wire type net to a wreal net.

Abstract: A computer implemented method is provided for use in evaluating a hierarchical representation of a circuit design encoded in a computer readable medium comprising: traversing a circuit path within a higher level circuit that includes a reference potential connection, to identify a port of a call to a first lower level circuit that is DC path connected to the reference potential; identifying a first DC port group that includes each port of the call to the first lower level circuit that is DC path connected to the identified port of the call to the first lower level circuit; automatically marking as DC path connected to the reference potential, each port of the call to the first lower level circuit that is a member of the first DC port group; and traversing a circuit path within the first lower level circuit to identify a circuit path within the first lower level circuit that is DC path connected to a marked port of the first lower level circuit.

Abstract: Various systems and methods related to semiconductor devices having a plurality of layers and having a first conductive trace on a first layer electrically connected to a second conductive trace on a second layer and electrically isolated from a third electrical trace on the second layer are provided. A semiconductor structure can include first, second and third layers. The first conducting layer may be etched to form a first trench for the first conductive trace. A layer of material on the second layer in the first trench can define a patch area, wherein the patch area is disposed in a location where the first trench crosses over the third electrical trace. A second trench may be etched in an area defined by the first trench and the patch area to remove material in the second layer exposed by the first trench, leaving material of the layer under the patch area.

Abstract: Systems and methods for modeling a multilayer integrated circuit include three-dimensional interconnect models in multilayered substrates for greater accuracy. Mesh models are used to resolve effects of nearby elements and grid models are used to resolve effects of far-away elements. Sidewall mesh elements of three-dimensional interconnects are projected onto parallel (or substantially parallel) grids between the top and bottom walls of the interconnects so that grid models can be used to resolve three-dimensional effects of interconnects in multilayered substrates.

Abstract: The present invention provides a method for generating flat layout design view that comprises importing port definitions of a first hierarchical block of digital instances from a source as a schematic symbol, importing port definitions of digital instances within the first hierarchical block from the source, instantiating the schematic symbol as a hierarchical layout instance in the flat layout, binding the hierarchical layout instance to the schematic symbol, and embedding digital layout block instances within the design layout by replacing the digital instances of a digital layout block with digital layout instances of a top layout module of the design layout.

Abstract: Routing methods for an integrated circuit design layout are disclosed. The layout can include design netlists and library cells. A multiple-level global routing can generate topological wire for each net. An area oriented graph-based detail routing on the design can be performed. A post route optimization after the detail routing can be performed to further improve the routing quality. Some methods can be single threaded all or some of the time, and/or multi-threaded some or all of the time.

Abstract: A routing method for a multilayer circuit design layout that has a set of possible preferred local routing directions and a default preferred routing direction for each layer. The method receives a set of user specified constraints on routing directions for particular regions of the design layout. The method tessellates the available routing space into separate tiles and automatically defines a preferred local routing direction for each tile based on the user specified constraints. The set of user specified constraints includes user designated flows, locked etches, “etch keep-out” areas, user “planned” data, etc. A routing method for a multilayer design layout that receives a first set of user specified preferred routing directions for particular regions of the multilayer design layout. The method tessellates the available routing space into separate tiles and automatically defines a second preferred local routing direction for each tile based on the user specified preferred routing directions.

Abstract: Method and system for managing a distributed computing environment. The methods and systems include handling multiple heterogeneous dispatch systems, preventing deadlock in single threaded servers, optimizing distributed activities, homogeneous identification of heterogeneous resources and automatically distributing failed tasks within a distributed system.

Abstract: A method for defining and producing a power grid structure (having stripe, rail, and via components) of an IC. The method reduces the number of vias in the power grid structure and the diagonal wiring blockage caused by the vias while still meeting design specifications. Other embodiments provide a method for locating vias in the power grid structure in such a way as to be especially beneficial to 45° or 135° diagonal wiring paths. The method includes processes of a power grid planner, power grid router, power grid verifier, and global signal router that are used iteratively to define and produce a power grid structure. Other embodiments of the invention provide for arrangements of vias in via arrays where diagonal wiring paths are facilitated near the edges of the via arrays. A bounding box enclosing these via arrays have an aspect ratio that is approximately equal to 1.

Abstract: A method is provided to evaluate crosstalk effect of aggressor switching upon victim net signal transition time within an integrated circuit comprising: combining a first probability density function (PDF) of first aggressor switching time in response to a first input signal to an aggressor net driver and a second aggressor switching time in response to a second input signal to the aggressor net driver; determining a delay change curve that represents a relationship between delay change of arrival time of a victim net signal transition and relative alignment of the aggressor net driver switching time and a victim net driver switching time; and determining a third PDF of delay change of a transition of the victim net signal based upon the combination and the delay change curve.