Abstract: In one embodiment of the invention, a method for electronic circuit design is disclosed.

Abstract: The debug system described in this patent specification provides a system that generates hardware elements from normally non-synthesizable code elements for placement on an FPGA device. This particular FPGA device is called a Behavior Processor. This Behavior Processor executes in hardware those code constructs that were previously executed in software. When some condition is satisfied (e.g., If . . . then . . . else loop) which requires some intervention by the workstation or the software model, the Behavior Processor works with an Xtrigger device to send a callback signal to the workstation for immediate response.

Abstract: A system and method are disclosed for waveform based variational static timing analysis. A circuit is divided into its linear circuit parts and non-linear circuit parts and modeled together, by a combination of linear modeling techniques, into linear equations that may be represented by matrices. The linear equations in matrix form may be readily solved by a computer such that an input waveform to an input pin of the circuit can be sequentially “pushed” through the various interconnects and logic networks of the circuit to an output pin. Output voltage waveforms are obtained at each stage of the waveform pushing and may be used to perform static timing analysis.

Abstract: Method and system for gathering and propagating statistical information about resources in a distributed computing grid. Data relating to a resource in the first group of resources on the distributed computing grid is received by a gatherer. The received data is provided to other resources in the first group, and a statistical model is determined or generated for each resource in the first group based on the received data. A second group of resources on the grid is called, and the statistical information from the first group is propagated to the second group.

Abstract: Disclosed are a method, a system, and a computer program product for implementing interactive cross-domain package driven I/O planning and placement optimization of an electronic circuit design. In some embodiments, the method identifies an object on a first EDA tool session, determines a drop location for the first object based on a tentative location in the first EDA tool session, places the first object at the drop location, and adjusts the drop location via a second EDA tool session, performs placement or routing of a portion of the design. The method or the system further comprises placing a corresponding first object in the second EDA tool session, initiating the second EDA tool session object move in the first EDA tool session, determining whether a constraint is satisfied.

Abstract: A circuit design process is presented that includes a block placement operation, followed by global routing based upon the initial placement of the blocks. Congestion data is generated from the global routing and, in an automated process, the blocks are placed again based upon the congestion data to reduce the routing congestion of the design. This can be used as part of a custom layout design process, for example.

Abstract: In one embodiment of the invention, a method of analysis of a circuit design is disclosed to generate a statistical timing model. The method includes receiving a timing graph of a circuit including arcs with a statistical function of delay, slew, or arrival time; determining primary input ports and output ports of the circuit; identifying timing pins between the input ports and the output ports of the circuit; and evaluating the timing pins from input ports to output ports to reduce the timing graph to ease analysis of the reduced timing graph with a processor.

Abstract: A method to create an integrated circuit that includes digital and analog components comprising: displaying on a computer system display, user input to the computer system that specifies parameter information to determine a binding between an analog circuit design component and a digital circuit design component; saving the user specified parameter information within a file that also specifies at least a portion of the analog circuit design; associating the analog circuit design component a first design block of an integrated circuit that also includes a second digital design block coupled to the first design block; using parameter information to determine a binding between the first analog circuit design component and the first digital circuit design component; saving the determined binding in computer readable storage media.

Abstract: A method to create an integrated circuit that includes digital and analog components comprising: displaying on a computer system display, user input to the computer system that specifies parameter information to determine a binding between an analog circuit design component and a digital circuit design component; saving the user specified parameter information within a file that also specifies at least a portion of the analog circuit design; associating the analog circuit design component a first design block of an integrated circuit that also includes a second digital design block coupled to the first design block; using parameter information to determine a binding between the first analog circuit design component and the first digital circuit design component; saving the determined binding in computer readable storage media.

Abstract: A system, method, and computer program product is disclosed that recycle digital assertions for mixed-signal electronic designs. The approach enables the re-use of pure digital assertions which reference signals that turn out to resolve to analog due to the particular circuit configuration chosen during the verification process.

Abstract: Disclosed is a method and system for performing design and verification using stepwise refinement techniques, which can also include or be referred to as “top-down” design verification. With the present stepwise refinement approach, the electronic design can be acted upon at different levels of abstraction, but with approximately the same level of resolution at each abstraction level. A strong relationship of consistency exists between the successive abstraction levels of the design. On account of this consistency, properties that are established or true at one level of the design remain true for all subsequent levels of abstraction of the design. The present approach also allows designers to more efficiently and accurately perform hardware/software co-design. For the co-design process, consistency between different levels of abstraction allows a designer to safely implement a systematic and concurrent divide-and-conquer approach to the hardware and/or software elements in a design.

Abstract: DFM systems are provided that incorporate manufacturing variations in the analysis of integrated circuits by calculating predicted manufacturing variations on the shapes of interconnects and devices of the drawn layout of a circuit design. The shape variation on interconnects is converted to variations in resistor-capacitor (RC) parasitics. The shape variation on devices is converted to variations in device parameters. The variation in device parameters and wire parasitics is converted to changes in timing performance, signal integrity, and power consumption by determining the impact of device parameter and wire parasitic variations on the behavior of each instance of a standard cell. The results from these analyses are integrated back into the design flow as incremental delay files (timing), noise failures and buffer insertion/driver resizing commands (noise), and leakage power hotspots and cell substitution commands (power consumption).

Abstract: A method and mechanism for implementing a general purpose scripting language that supports parallel execution is described. In one approach, parallel execution is provided in a seamless and high-level approach rather than requiring or expecting a user to have low-level programming expertise with parallel processing languages/functions. Also described is a system and method for performing circuit simulation. The present approach provides methods and systems that create reusable and independent measurements for use with circuit simulators. Also disclosed are parallelizable measurements having looping constructs that can be run without interference between parallel iterations. Reusability is enhanced by having parameterized measurements. Revisions and history of the operating parameters of circuit designs subject to simulation are tracked.

Abstract: For an integrated circuit associated with a plurality of parameters whose values are described by a first probability distribution function, a method for estimating a failure probability includes selecting a first plurality of samples, performing a first test to determine an outcome for each of the first plurality of samples and identifying failed samples, and clustering the failed samples using a computer-implemented cluster forming method that, in some cases, returns multiple clusters. The method also includes forming a probability distribution function for each of the clusters, forming a composite probability distribution function that includes a weighted combination of the first probability distribution function and the probability distribution function for each of the clusters. The method further includes selecting a second plurality of samples using the composite probability distribution function and performing a second test to determine an outcome for each of the second plurality of samples.

Abstract: A method, system, and computer program product are disclosed for performing RC extraction from the perspective of the block level. A translation mechanism is employed to convert from a full-chip design domain to a block-level design domain. This allows model-based prediction results to be used in the early design implementation flow when parasitic RC and timing extractions are performed, where the model-based prediction results relate to predictions of manufacturing variations such as thickness and topography.

Abstract: Certain embodiments of the present invention enable a user to display and edit the effects of inherited connections in a circuit that is characterized as a hierarchical arrangement including cell instances and connectors. The hierarchical arrangement may include a tree structure where the cell instances include devices and the connectors include wires and pins. Property names are associated with connectors for identifying corresponding signal sources, and property-setting expression are associated with cell instances for specifying property-name values and making the corresponding identifications. Displays may include a path along the hierarchical arrangement from a given connector to a corresponding signal source including the effects of property names and property-setting expressions along the path. Displays may enable editing by the user to change property names and property-setting expressions along the path and view corresponding results for the inherited connections.

Abstract: In some embodiments of the invention, a method and apparatus of consolidating all types of coverage metrics, obtained from an HDL simulator, under a single common framework is described. In other embodiments of the invention, a method and an apparatus are disclosed for performing ranking from a verification plan using total coverage metric.

Abstract: An extensible design verification system and methods thereof are disclosed. Pre-defined constraints from an integrated verification application are registered with a core which manages the verification system. The core is utilized by the integrated verification application to execute one or more verification tasks to generate a result. The result can be captured by a user interface. Constraints and the user-interface can be either pre-defined or user-defined. User-defined constraints and interface are managed in the same manner as those that are pre-defined. The user-defined constraints and interface are exportable for reuse by other designs.

Abstract: Some embodiments provide a method for decomposing a region of an integrated circuit (“IC”) design layout into multiple mask layouts. The method identifies a number of sets of geometries in the design layout region that must be collectively assigned to the multiple mask layouts. The method assigns the geometries in a first group of collectively-assigned sets to different mask layouts without splitting any of the geometries. The method assigns the geometries in a second group of the collectively-assigned sets to different mask layouts in such a way so as to minimize the number of splits in the geometries of the second group.

Abstract: Certain embodiments of the present invention enable comparisons between constrained circuit designs by generating timing graphs for circuit designs, mapping timing constraints to the timing graphs, and comparing the mapped timing constraints from different timing graphs. Typically this comparison is made by identifying corresponding nodes in two or more timing graphs. Specific embodiments are also directed to multiple SDC (Synopsis Design Constraint) constraint specifications for a circuit and multiple constraint sets for different operational modes of a circuit.