Patents Assigned to Cadence Design Systems
  • Patent number: 8141008
    Abstract: A apparatus and method for correcting a process critical layout includes characterizing the influence of individual ones of a set of worst case process variations on a simulated nano-circuit layout design and then correcting layout geometries in the simulated nano-circuit layout based on such characterizations.
    Type: Grant
    Filed: December 17, 2010
    Date of Patent: March 20, 2012
    Assignee: Cadence Design Systems, Inc.
    Inventor: Franz Xaver Zach
  • Patent number: 8136060
    Abstract: A method and mechanism is disclosed for identifying and tracking nets in an electrical design. A hierarchical design does not have to be flattened to perform the operation of identifying and tracking nets. To identify sets of connected shapes, instead of having to unfold the entire design hierarchy, only the specific instances of shapes falling within the geometric bounds of shapes identified as being part of a net needs to be unfolded to perform the search. When composing the list of nets for a hierarchical design, the unfolded shapes at other hierarchical levels of the design can be derived based upon virtual terminal structures that implicitly references nets and objects at other levels.
    Type: Grant
    Filed: December 29, 2009
    Date of Patent: March 13, 2012
    Assignee: Cadence Design Systems, Inc.
    Inventor: Eric Nequist
  • Patent number: 8136068
    Abstract: Disclosed are a method, a system, and a computer program product for implementing compact manufacturing model during various stages of electronic circuit designs. In some embodiments, the method or the system receives or identifies physics based data. In some embodiments, the method or the system receives or identifies the physics based data for the corresponding manufacturing process by using the golden manufacturing process model. In some embodiments, the method or the system uses the physics based data to fine tune, modify, or adjust the golden manufacturing process model. In some embodiments, the method or the system invokes the just-right module. In some embodiments, the method or the system implements the compact manufacturing model and the correct-by-design module and provides guidelines for the various stages of the electronic circuit design.
    Type: Grant
    Filed: September 30, 2008
    Date of Patent: March 13, 2012
    Assignee: Cadence Design Systems, Inc.
    Inventors: Li J. Song, Srini Doddi, Emmanuel Drego, Nickhil Jakatdar
  • Patent number: 8136056
    Abstract: Methods and systems for representing the limitations of a lithographic process using a pattern library instead of, or in addition to, using design rules. The pattern library includes “known good” patterns, which chip fabricators know from experience are successful, and “known bad” patterns, which chip fabricators know to be unsuccessful. The pattern library can be used to contain exceptions to specified design rules, or to replace the design rules completely. In some implementations, the pattern library contains statistical information that is used to contribute to an overall figure of merit for the design. In other implementations, a routing tool may generate a plurality of possible IC layouts, and select one IC layout based on information contained in the pattern library.
    Type: Grant
    Filed: May 19, 2006
    Date of Patent: March 13, 2012
    Assignee: Cadence Design Systems, Inc.
    Inventors: Louis K. Scheffer, David C. Noice
  • Patent number: 8132135
    Abstract: A system, method, computer program product for verification and equivalence checking. In one approach, the system, method, and computer program product analyzes the switching paths in a manner consistent with circuit functionality to provide a complete application which can verify the complex characteristics in the circuits to the accurate RTL model function, including FPGA, ROM Arrays, RAM circuits, and other custom integrated circuit designs.
    Type: Grant
    Filed: October 29, 2008
    Date of Patent: March 6, 2012
    Assignee: Cadence Design Systems, Inc.
    Inventors: Kei-Yong Khoo, Mitchell Hines, Chih-Chang Lin
  • Patent number: 8127260
    Abstract: In one embodiment of the invention, a physical layout wire-load algorithm is used to generate a wire-load model based on physical data including aspect ratio and wire definitions defined in a physical library. The physical layout estimator is utilized to dynamically produce the physical layout wire-load model and to calculate net length and delay for each optimization iteration.
    Type: Grant
    Filed: December 1, 2006
    Date of Patent: February 28, 2012
    Assignee: Cadence Design Systems, Inc.
    Inventors: Hurley Song, Denis Baylor, Matthew Robert Rardon
  • Patent number: 8122397
    Abstract: Aspects for optimized mapping of source elements to destination elements as interconnect routing assignments are described. The aspects include utilizing chosen rules to establish a priority for mapping, and generating mapping assignments based on the priority. The mapping assignments are recursively refined to converge on an optimized solution.
    Type: Grant
    Filed: December 9, 2008
    Date of Patent: February 21, 2012
    Assignee: Cadence Design Systems, Inc.
    Inventors: Tyler J. Lockman, Phuong Ha-Uyen Landry
  • Patent number: 8122389
    Abstract: An apparatus and method for modifying a mask data set includes calculating a derivative of a figure-of-merit, indicative of a data set defined by a plurality of polygon edges and then segmenting polygon edges in response to said step of calculating.
    Type: Grant
    Filed: January 20, 2010
    Date of Patent: February 21, 2012
    Assignee: Cadence Design Systems, Inc.
    Inventors: Abdurrahman Sezginer, Bayram Yenikaya, Hsu-Ting Huang
  • Patent number: 8120378
    Abstract: Systems, methods, and computer readable media storing instructions for such methods relate to generating test vectors that can be used for exercising a particular area of interest in an integrated circuit. The test vectors generally include a non-overlapping repeating and/or predictable sequence of care bits (a care bit pattern) that can be used by a tester to cause the exercise of the area and collect emissions caused by exercising the area. Such emissions can be used for analysis and debugging of the circuit and/or a portion of it. Aspects can include providing a synchronization signal that can be used by a tester to allow sensor activation at appropriate times.
    Type: Grant
    Filed: August 31, 2010
    Date of Patent: February 21, 2012
    Assignee: Cadence Design Systems, Inc.
    Inventors: Joseph Swenton, Thomas Bartenstein, Richard Schoonover, David Sliwinski
  • Patent number: 8122392
    Abstract: The present invention allows for a robust design using manufacturability models. A method, system and/or computer usable medium may be provided in an integrated circuit design to track sensitivity to a variation of process from wafer to wafer and/or fab to fab in order to assist the designers to anticipate the variations to improve the final yield of the products.
    Type: Grant
    Filed: June 26, 2008
    Date of Patent: February 21, 2012
    Assignee: Cadence Design Systems, Inc.
    Inventors: David White, Louis K. Scheffer
  • Patent number: 8117566
    Abstract: A mechanism to compress manufacturing awareness into a small representation and to enable the router to consult the representation without performing, or understanding, detailed process analysis, is disclosed.
    Type: Grant
    Filed: November 21, 2008
    Date of Patent: February 14, 2012
    Assignee: Cadence Design Systems, Inc.
    Inventor: Louis Scheffer
  • Patent number: 8117569
    Abstract: Disclosed is an improved method, system, and mechanism for using and constructing a minimum spanning tree. In one approach, each iteration of the process for constructing a minimum spanning tree calculates at most two additional point-pairs for nearest neighbors of points previously added to the tree. These additional point-pairs are appended to a list of point pairs, and the point-pair having the shortest distance is selected and added to the minimum spanning tree. Any metric can be employed to determine nearest neighbors, including Euclidean or Manhattan metrics. An advantage is that not all point-pairs need to be examined, greatly increasing speed and efficiency. Since every point-pair does not have to be examined, a preprocessing step is not required to reduce the number of point-pairs being considered. The resultant minimum spanning tree can be used to facilitate the routing process for an integrated circuit.
    Type: Grant
    Filed: December 29, 2009
    Date of Patent: February 14, 2012
    Assignee: Cadence Design Systems, Inc.
    Inventor: Jeffrey Scott Salowe
  • Patent number: 8112733
    Abstract: Some embodiments of the invention provide a method of routing. The method selects a net with a set of routable elements in a multi-layer layout region. In some embodiments, the method identifies a route for the net based on different congestion goals on different layers. In other embodiments, the method identifies a route for the net based on different congestion goals between different layer pairs. In some embodiments, the method identifies a route for the net based on both the different congestion goals on different layers and between different layer pairs.
    Type: Grant
    Filed: December 1, 2008
    Date of Patent: February 7, 2012
    Assignee: Cadence Design Systems, Inc.
    Inventors: Jonathan Frankle, Andrew Caldwell
  • Patent number: 8108194
    Abstract: A method of analyzing power consumption for a DUT (device under test) that includes an integrated circuit or an electronic system includes: providing emulation data for states of the DUT in one or more time windows; determining operational mode values from the emulation data and a selection of operational modes that characterize circuit behavior in the one or more time windows; dividing each time window into one or more segments based on at least one power criterion; determining power-activity values for the one or more segments; determining power-consumption values for the one or more segments from the power-activity values; using the power-activity values and the power-consumption values to determine relative power activity across the one or more segments and adjusting the one or more segments to target high power activity over operational modes in the one or more time windows; and saving one or more values for power activity of the DUT in a computer-readable medium.
    Type: Grant
    Filed: December 30, 2008
    Date of Patent: January 31, 2012
    Assignee: Cadence Design Systems, Inc.
    Inventors: Bing Zhu, Tsair-Chin Lin, Tung-sun Tung, Jingbo Gao
  • Patent number: 8108878
    Abstract: Method and system for detecting indeterminate dependencies in a distributed computing grid. A determination is made whether a deadlock situation exists within a workflow of the distributed computing grid and a user of the computing grid is notified of the deadlock situation, e.g., where in the workflow deadlock occurs. A deadlock situation can be determined based on direct and indirect dependencies, such as loops and dependencies involving a first work element and a lower level second work element. A deadlock situation can also be determined based on the relationships between a job and a task, which is executable by a processor in the distributed computing grid.
    Type: Grant
    Filed: December 8, 2005
    Date of Patent: January 31, 2012
    Assignee: Cadence Design Systems, Inc.
    Inventor: Darren W. Pulsipher
  • Patent number: 8104007
    Abstract: Some embodiments of the invention provide a method for performing thermal analysis of an integrated circuit (“IC”) design layout that includes numerous circuit modules. The method divides the IC design layout into a set of elements, where at least one element includes several wires. The method computes a set of conductivity groups of values for the set of elements. The method identifies a temperature distribution for the IC design layout based on the set of conductivity groups of values. In some embodiments, each of these elements corresponds to a particular portion of a particular layer of the IC design layout. Each element includes several nodes. Each conductivity group of values is defined by entry values. Each entry value describes how heat flow at a particular node of the element is affected by a temperature change at another particular node of the element.
    Type: Grant
    Filed: June 24, 2008
    Date of Patent: January 24, 2012
    Assignee: Cadence Design Systems, Inc.
    Inventors: Vinod Kariat, Eddy Pramono, Yong Zhan
  • Patent number: 8103996
    Abstract: Some embodiments of the invention provide a method for performing thermal analysis of an integrated circuit (“IC”) design layout. The IC design layout includes several wiring layers in some embodiments. The IC design layout includes a substrate that has at least one through-silicon via (“TSV”). The method divides the IC design layout into a set of elements. The method identifies a temperature distribution for the IC design layout by using the set of elements. In some embodiments, at least one element includes a metal component and a non-metal component. The non-metal component is silicon in some embodiments, and a dielectric in other embodiments.
    Type: Grant
    Filed: April 1, 2009
    Date of Patent: January 24, 2012
    Assignee: Cadence Design Systems, Inc.
    Inventors: Vinod Kariat, Eddy Pramono, Yong Zhan
  • Patent number: 8103985
    Abstract: Disclosed is a method, system, and computer program product for implementing controlled breaks using sub-resolution assist features. Sub-resolution bridging features are added to implement controlled breaks between features on the layout. The bridging features may also be used to facilitate or optimize multiple mask/exposure techniques that split a layout or features on a layout to address pitch problems.
    Type: Grant
    Filed: November 2, 2007
    Date of Patent: January 24, 2012
    Assignee: Cadence Design Systems, Inc.
    Inventor: Jason Sweis
  • Patent number: 8103986
    Abstract: A mechanism to compress manufacturing awareness into a small representation and to enable the router to consult the representation without performing, or understanding, detailed process analysis, is disclosed.
    Type: Grant
    Filed: November 21, 2008
    Date of Patent: January 24, 2012
    Assignee: Cadence Design Systems, Inc.
    Inventor: Louis Scheffer
  • Patent number: 8104001
    Abstract: An automated debugging method and system for over-constrained circuit verification environment are described. Useful information related to circuit evaluation and/or over-constrained event is collected and provided. The information may include: clock cycles at which an over-constrained event occurs; identification of a minimum subset of constraints that will cause an over-constrained event to occur; signal ports having an associated signal that can not switch between different signal states; whether a triggering signal event has occurred during the evaluation; indicating whether constraints in the evaluation are realizable, etc. Novel approaches for detecting and obtaining the useful information also are described.
    Type: Grant
    Filed: October 31, 2008
    Date of Patent: January 24, 2012
    Assignee: Cadence Design Systems, Inc.
    Inventors: Amir Lehavot, Vinaya Kumar Singh, Joezac John Zachariah, Jose Barandiaran, Axel Siegfried Scherer